Emil J
378add3723
Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak
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simplify: fix single_bit_vector memory leak
2025-06-04 17:00:54 +02:00
George Rennie
0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
George Rennie
ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix
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read_verilog: fix -1 constant used to correct post increment/decrement
2025-06-04 14:22:32 +01:00
Emil J. Tywoniak
c37b7b3bf4
simplify: fix single_bit_vector memory leak
2025-06-04 10:32:03 +02:00
George Rennie
45e8ff476e
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 01:09:03 +01:00
KrystalDelusion
545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global
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SystemVerilog: Fix typedef struct in global space
2025-05-31 09:59:26 +12:00
George Rennie
70291f0e49
read_verilog: fix -1 constant used to correct post increment/decrement
2025-05-30 14:38:25 +01:00
KrystalDelusion
489a12d6c1
Merge pull request #5141 from garytwong/unique-if
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Accept (and ignore) SystemVerilog unique/priority if.
2025-05-27 09:45:50 +12:00
Krystine Sherwin
32ce23458f
read_verilog: Mark struct as custom type
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Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
2025-05-26 12:19:33 +12:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Gary Wong
9770ece187
Accept (and ignore) SystemVerilog unique/priority if.
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Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.
This affects only the grammar accepted; the behaviour of conditionals
is not changed. (But accepting this syntax will provide scope for
possible optimisations as future work.)
Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
2025-05-22 19:28:28 -06:00
Emil J. Tywoniak
e5171d6aa1
verific: support single_bit_vector
2025-05-12 13:23:29 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
Krystine Sherwin
fe0abb7026
simplify.cc: Fix mem leak
2025-05-10 17:10:47 +12:00
Krystine Sherwin
23cb007068
verilog_parser.y: Delete unused TOK_ID
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Fixes memory leak when parameter has no value.
2025-05-05 10:04:13 +12:00
N. Engelhardt
8bdbf797d0
Merge pull request #5017 from YosysHQ/micko/ram_blasting
2025-04-28 13:33:48 +00:00
Emil J. Tywoniak
bdc2597f79
simplify: fix struct wiretype attr memory leak
2025-04-25 01:00:08 +02:00
Miodrag Milanovic
22e6ce4282
verific: bit blast RAM if using mem2reg attribute
2025-04-14 15:24:11 +02:00
Miodrag Milanovic
406ee4c8d3
read_verilog_file_list: change short help message to start with lower case
2025-04-08 13:20:16 +02:00
Jannis Harder
0f13b55173
Liberty file caching with new libcache command
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This adds optional in-memory caching of parsed liberty files to speed up
flows that repeatedly parse the same liberty files. To avoid increasing
the memory overhead by default, the caching is disabled by default. The
caching can be controlled globally or on a per path basis using the new
`libcache` command, which also allows purging cached data.
2025-04-03 13:39:35 +02:00
Miodrag Milanovic
72f2185a94
verific: fix restoring msg state after blackbox import
2025-04-01 17:35:59 +02:00
Emil J. Tywoniak
813f909460
gzip: istream
2025-03-19 13:43:44 +01:00
Emil J. Tywoniak
4f3fdc8457
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
Jason Xu
a5f34d04f8
Address comments
2025-03-11 18:50:44 -04:00
Jason Xu
98eefc5d1a
Add file list support to read pass
2025-03-07 20:44:21 -05:00
Jason Xu
bf1eab565b
Fix compile on WASI platform
2025-03-07 20:20:27 -05:00
Jason Xu
ac31bad656
Address all comments
2025-03-07 20:16:28 -05:00
Jason Xu
8ec96ec806
Address most comments
2025-03-07 20:16:28 -05:00
Jason Xu
0678c4dec9
Coding style update
2025-03-07 20:16:28 -05:00
Jason Xu
f62a9be153
Initial file list support
2025-03-07 20:16:28 -05:00
Emil J
39aacc95df
Merge pull request #4907 from YosysHQ/emil/fix-clear-preset-latch
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liberty: fix clear and preset latches
2025-03-03 18:53:12 +01:00
Martin Povišer
732ed67014
ast/dpicall: Stop using variable length array
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Fix the compiler warning
variable length arrays in C++ are a Clang extension [-Wvla-cxx-extension]
2025-02-24 17:32:30 +01:00
Emil J. Tywoniak
2b33937ab8
liberty: fix clear and preset latches
2025-02-17 17:36:51 +01:00
KrystalDelusion
cf52cf3009
nowrshmsk: Check for stride==0
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log2(0) returns -inf, which gives undefined behaviour when casting to an int. So catch the case when it's 0 just set the width to 0.
2025-01-31 12:15:53 +13:00
N. Engelhardt
d640157ec4
fix some cases of hdlname being added to objects with private names
2025-01-15 15:56:42 +01:00
Emil J. Tywoniak
a58481e9b7
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
Emil J. Tywoniak
b9b9515bb0
hashlib: hash_eat -> hash_into
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854
hashlib: acc -> eat
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
N. Engelhardt
378864d33b
bound attributes: handle vhdl null ranges
2024-12-12 11:42:39 +01:00
N. Engelhardt
03033ab6d4
add more tests for bounds attributes, fix attributes appearing in verilog
2024-12-11 16:11:02 +01:00
Martin Povišer
ea38fcca5e
Merge pull request #4737 from povik/abc_new-design-boxes
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Support `abc9_box` on ordinary modules in abc_new
2024-12-10 20:07:56 +01:00
Martin Povišer
e9c7967d1e
Merge pull request #4804 from povik/read_liberty-comb-cells
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read_liberty: Revisit for abc9 whiteboxes
2024-12-10 17:50:21 +01:00
Martin Povišer
6b343c2600
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
Martin Povišer
a353b8fff0
read_liberty: Directly set abc9_box on fitting cells
2024-12-09 15:43:41 +01:00
Miodrag Milanovic
7d4aff618f
verific: Disable module existence check during static elaboration
2024-12-06 15:59:09 +01:00
Martin Povišer
cf0a583f40
read_xaiger2: Rm debug print
2024-12-05 18:33:20 +01:00
Martin Povišer
5dffdd229c
read_liberty: Redo unit delay; add simple_comb_cell attr
2024-12-05 18:31:24 +01:00
KrystalDelusion
c96d02b204
Merge pull request #4784 from YosysHQ/krys/reduce_warnings
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Reduce number of warnings
2024-12-05 09:16:06 +13:00
Krystine Sherwin
e634e9c26b
aiger2: Resolve warnings
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- Remove unused statics CONST_FALSE and CONST_TRUE (which appear to have been folded into the `Index` declaration as CFALSE and CTRUE).
- Assign default value of EMPTY_LIT to `a` and `b` for comparison ops.
- Tag debug only variables with YS_MAYBE_UNUSED, don't assign unused variables (but continue to call the function because it moves the file pointer).
2024-12-03 14:01:57 +13:00
