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6878 commits 121 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
c9ab18889a synth_xilinx to now have shregmap call after dff2dffe 2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048 Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 2019-02-28 09:31:24 -08:00
Clifford Wolf
63be3f3bab Improvements in "supercover" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-27 11:45:13 -08:00
Clifford Wolf
a58dbcf2ba Add "supercover" skeleton 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-27 11:37:08 -08:00
Abdelrahman
3e3b115e0f add dockerignore file 2019-02-26 21:02:02 -05:00
Abdelrahman
0a94441579 dockerize yosys 2019-02-26 20:53:31 -05:00
Eddie Hung
f7c7003a19 Merge remote-tracking branch 'origin/master' into xaig 2019-02-26 13:16:03 -08:00
Eddie Hung
dfb23a79dd Uncomment out more tests 2019-02-26 12:18:48 -08:00
Eddie Hung
7cac3b1c8b abc9 -- multiple connections for inouts 2019-02-26 12:18:28 -08:00
Eddie Hung
8e883d92ed write_xaiger to behave for undriven/unused inouts 2019-02-26 12:17:51 -08:00
Eddie Hung
da076344cc parse_xaiger() to really pass single and multi-bit inout tests 2019-02-26 12:04:45 -08:00
Eddie Hung
3ea0161ae7 Add IdString::ends_with() 2019-02-26 12:04:16 -08:00
Eddie Hung
66b5f5166b Enable two inout tests 2019-02-26 11:39:17 -08:00
Eddie Hung
8f02c846f6 parse_xaiger() to cope with multi bit inouts 2019-02-26 11:37:34 -08:00
Larry Doolittle
7a40294e93 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d Clean up some whitepsace outliers 2019-02-26 09:39:46 -08:00
Eddie Hung
967297cd57 abc9 cleanup 2019-02-25 18:40:53 -08:00
Eddie Hung
316232a7dd parse_xaiger() to untransform $inout.out output ports 2019-02-25 18:40:23 -08:00
Eddie Hung
c492a3a1c4 write_xaiger duplicate inout port into out port with $inout.out suffix 2019-02-25 18:39:36 -08:00
Jim Lawson
171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment. 
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
 2019-02-25 16:18:13 -08:00
Jim Lawson
81abb2517c Merge remote-tracking branch 'upstream/master' 2019-02-25 16:04:20 -08:00
Eddie Hung
721f6a14fb read_aiger to accept empty string for clk_name, passable only if no latches 2019-02-25 15:34:02 -08:00
Eddie Hung
0ca3fd6a1c abc9 not to clean after aigmap 2019-02-25 15:31:52 -08:00
Eddie Hung
292f80d231 Cleanup abc9 code 2019-02-25 15:20:56 -08:00
Eddie Hung
65c8ccf7b5 Add broken testcases 2019-02-25 15:06:23 -08:00
Eddie Hung
51f28a6747 abc9 to call "clean" once at the end of all abc9_module() calls 2019-02-25 12:55:47 -08:00
David Shah
fa2f595cfa ecp5: Compatibility with Migen AsyncResetSynchronizer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-25 13:24:30 +00:00
Clifford Wolf
c258b99040 Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:41:36 +01:00
Clifford Wolf
c118f9a377
Merge pull request #812 from ucb-bar/arrayhierarchyfixes 
Define basic_cell_type() function and use it to derive the cell type …
 2019-02-24 11:39:13 -08:00
Clifford Wolf
cd722f26a5 Cleanups in ARST handling in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:34:23 +01:00
Clifford Wolf
da14bc8524
Merge pull request #824 from litghost/fix_reduce_on_ff 
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
 2019-02-24 11:29:14 -08:00
Clifford Wolf
1816fe06af Fix handling of defparam for when default_nettype is none 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:09:41 +01:00
Clifford Wolf
a516b4fb5a Check if Verific was built with DB_PRESERVE_INITIAL_VALUE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 19:51:30 +01:00
Jim Lawson
71bcc4c644 Address requested changes - don't require non-$ name. 
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
 2019-02-22 16:06:10 -08:00
Keith Rothman
25680f6a07 Fix WREDUCE on FF not fixing ARST_VALUE parameter. 
Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-22 10:30:42 -08:00
Clifford Wolf
c521f4632f
Merge pull request #819 from YosysHQ/clifford/optd 
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
 2019-02-22 06:55:48 +01:00
Clifford Wolf
25a3a96107
Merge pull request #820 from YosysHQ/clifford/fix810 
Fix #810 and fix #814
 2019-02-22 06:54:48 +01:00
Eddie Hung
d56f02d1fc abc9 to use AIGER symbol table, as opposed to map file 2019-02-21 17:03:40 -08:00
Eddie Hung
5180338e80 write_xaiger to write __dummy_o__ for -symbols too 2019-02-21 17:03:18 -08:00
Eddie Hung
07036b8bf7 read_aiger to work with symbol table 2019-02-21 17:01:07 -08:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress 
Improve ABC netname preservation
 2019-02-22 01:16:34 +01:00
Clifford Wolf
362ef36ccd Fix Travis 
It looks like that whole "Fixing Travis's git clone" code was just
there to make the "git describe --tags" work. I simply removed both.

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-22 00:15:55 +01:00
Eddie Hung
2811d66dea Revert "abc9 to write_xaiger -symbols, not -map" 
This reverts commit 04429f8152.
 2019-02-21 14:58:40 -08:00
Eddie Hung
7ad9628f07 Remove irrelevant citations 2019-02-21 14:41:11 -08:00
Eddie Hung
085ed9f487 Add attribution 2019-02-21 14:40:13 -08:00
Eddie Hung
875a02a6f2 abc9 to not select anything extra, and pop selection after final clean 2019-02-21 14:38:52 -08:00
Eddie Hung
04429f8152 abc9 to write_xaiger -symbols, not -map 2019-02-21 14:28:36 -08:00
Eddie Hung
3307295488 Merge branch 'read_aiger' into xaig 2019-02-21 14:27:32 -08:00
Eddie Hung
d3ba1f9719 Merge branch 'read_aiger' of https://github.com/eddiehung/yosys into read_aiger 2019-02-21 14:17:48 -08:00
Eddie Hung
6ccaf250df Merge branch 'read_aiger' into xaig 2019-02-21 14:14:28 -08:00