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	abc9 to call "clean" once at the end of all abc9_module() calls
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					 1 changed files with 4 additions and 4 deletions
				
			
		|  | @ -409,6 +409,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri | |||
| 
 | ||||
|     Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str())); | ||||
| 
 | ||||
| 	design->selection_stack.pop_back(); | ||||
| 
 | ||||
| 	// Now 'unexpose' those wires by undoing
 | ||||
| 	// the expose operation -- remove them from PO/PI
 | ||||
| 	// and re-connecting them back together
 | ||||
|  | @ -919,8 +921,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri | |||
| 	//	log("Don't call ABC as there is nothing to map.\n");
 | ||||
| 	//}
 | ||||
| 
 | ||||
| 	Pass::call(design, "clean"); | ||||
| 
 | ||||
| cleanup: | ||||
| 	if (cleanup) | ||||
| 	{ | ||||
|  | @ -928,8 +928,6 @@ cleanup: | |||
| 		remove_directory(tempdir_name); | ||||
| 	} | ||||
| 
 | ||||
| 	design->selection_stack.pop_back(); | ||||
| 
 | ||||
| 	log_pop(); | ||||
| } | ||||
| 
 | ||||
|  | @ -1540,6 +1538,8 @@ struct Abc9Pass : public Pass { | |||
| 			} | ||||
| 		} | ||||
| 
 | ||||
|         Pass::call(design, "clean"); | ||||
| 
 | ||||
| 		assign_map.clear(); | ||||
| 		signal_map.clear(); | ||||
| 		signal_init.clear(); | ||||
|  |  | |||
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