Jim Lawson
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d6c4dfb902
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Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Mark dff_init.v as expected to fail since it uses "initial value".
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2019-03-04 13:37:23 -08:00 |
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Jim Lawson
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6d2ea6fe55
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Merge remote-tracking branch 'upstream/master'
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2019-03-04 12:55:02 -08:00 |
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Kali Prasad
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32a901ddf2
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Added examples/anlogic/
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2019-03-04 23:26:56 +05:30 |
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Keith Rothman
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228f132ec3
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Revert BRAM WRITE_MODE changes.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-04 09:22:22 -08:00 |
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David Shah
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777864d02e
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ecp5: Demote conflicting FF init values to a warning
Signed-off-by: David Shah <dave@ds0.me>
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2019-03-04 11:26:20 +00:00 |
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Clifford Wolf
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107d884804
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Improve igloo2 example
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-03 23:54:35 -08:00 |
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Clifford Wolf
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a176ac95de
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Update igloo2 example to Libero v12.0
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-03 21:36:03 -08:00 |
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Clifford Wolf
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52f80718a7
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Merge pull request #848 from YosysHQ/clifford/fix763
Fix error for wire decl in always block, fixes 763
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2019-03-02 16:32:58 -08:00 |
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Clifford Wolf
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dddf837f69
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Merge pull request #849 from YosysHQ/clifford/dynports
Only run derive on blackbox modules when ports have dynamic size
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2019-03-02 16:01:31 -08:00 |
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Clifford Wolf
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ae9286386d
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Only run derive on blackbox modules when ports have dynamic size
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 12:36:46 -08:00 |
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Clifford Wolf
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3a51714451
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Fix error for wire decl in always block, fixes #763
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 11:56:44 -08:00 |
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Clifford Wolf
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ce6695e22c
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Fix $global_clock handling vs autowire
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 10:38:13 -08:00 |
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Clifford Wolf
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65412466c5
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Merge pull request #847 from YosysHQ/clifford/fix785
Fix $readmem[hb] for mem2reg memories, fixes #785
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2019-03-02 10:27:58 -08:00 |
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Clifford Wolf
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5d93dcce86
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Fix $readmem[hb] for mem2reg memories, fixes #785
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 09:58:20 -08:00 |
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Clifford Wolf
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f2f5ecd834
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Merge pull request #843 from YosysHQ/clifford/mem2regconstidx
Use mem2reg on memories that only have constant-index write ports
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2019-03-02 08:40:54 -08:00 |
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Clifford Wolf
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67b78ea4fb
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Merge pull request #845 from YosysHQ/clifford/travisnomacos
Disable macOS builds in Travis
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2019-03-02 08:40:17 -08:00 |
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Clifford Wolf
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f75aee87e3
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Disable macOS builds in Travis
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 08:29:28 -08:00 |
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Larry Doolittle
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57f8bb471f
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Try again for passes/pmgen/ice40_dsp_pm.h rule
Tested on both in-tree and out-of-tree builds
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2019-03-01 20:20:53 -08:00 |
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Abdelrahman
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ed358b237b
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address review comments
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2019-03-01 20:06:43 -05:00 |
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Keith Rothman
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3e16f75bc6
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Revert FF models to include IS_x_INVERTED parameters.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 14:41:21 -08:00 |
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Keith Rothman
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5ebeca12eb
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Use singular for disabling of DRAM or BRAM inference.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 14:35:14 -08:00 |
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Clifford Wolf
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a02d61576e
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Minor improvements in README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-01 14:29:17 -08:00 |
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Clifford Wolf
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7cfae2c52f
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Use mem2reg on memories that only have constant-index write ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-01 13:35:09 -08:00 |
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Clifford Wolf
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03237de686
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Fix "write_edif -gndvccy"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-01 12:59:07 -08:00 |
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Keith Rothman
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eccaf101d8
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Modify arguments to match existing style.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 12:14:27 -08:00 |
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Keith Rothman
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3090951d54
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Changes required for VPR place and route synth_xilinx.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 12:02:27 -08:00 |
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Clifford Wolf
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66fd6396d4
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Merge pull request #841 from mmicko/master
Fix ECP5 cells_sim for iverilog
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2019-03-01 10:53:23 -08:00 |
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Jim Lawson
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4cce7f6967
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Merge remote-tracking branch 'upstream/master'
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2019-03-01 10:31:26 -08:00 |
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Miodrag Milanovic
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ca2b3feed8
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Fix ECP5 cells_sim for iverilog
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2019-03-01 19:25:23 +01:00 |
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Clifford Wolf
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60e3c38054
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Improve "read" error msg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 20:34:42 -08:00 |
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Clifford Wolf
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a82a7eb42e
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Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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2019-02-28 20:27:27 -08:00 |
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Clifford Wolf
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b84febafd7
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Hotfix for "make test"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 20:26:54 -08:00 |
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Clifford Wolf
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35e7f9979e
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Merge pull request #837 from YosysHQ/clifford/fix835
Fix multiple issues in wreduce FF handling, fixes #835
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2019-02-28 17:40:38 -08:00 |
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Clifford Wolf
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e847690bda
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Fix multiple issues in wreduce FF handling, fixes #835
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 17:24:46 -08:00 |
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Elms
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cd2902ab1f
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
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2019-02-28 16:23:40 -08:00 |
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Clifford Wolf
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f505a41b76
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Merge pull request #834 from YosysHQ/clifford/siminit
Add "write_verilog -siminit"
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2019-02-28 15:03:55 -08:00 |
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Clifford Wolf
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241901461a
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Add "write_verilog -siminit"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 15:03:03 -08:00 |
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Larry Doolittle
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e2fc18f27b
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Reduce amount of trailing whitespace in code base
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2019-02-28 14:58:11 -08:00 |
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Clifford Wolf
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68a6937173
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Fix pmgen for in-tree builds
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 14:56:05 -08:00 |
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Clifford Wolf
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41e5028f98
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Merge pull request #794 from daveshah1/ecp5improve
ECP5 Improvements
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2019-02-28 14:46:56 -08:00 |
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Clifford Wolf
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6d143c9a01
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Merge pull request #827 from ucb-bar/firrtlfixes
Fix FIRRTL to Verilog process instance subfield assignment.
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2019-02-28 14:45:04 -08:00 |
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Clifford Wolf
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64d91219b4
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Fix pmgen for out-of-tree build
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 14:00:58 -08:00 |
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Eddie Hung
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1da0909662
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Remove SRL16/32 from cells_xtra
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2019-02-28 13:56:45 -08:00 |
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Eddie Hung
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73ddab6960
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Add SRL16 and SRL32 sim models
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2019-02-28 13:56:22 -08:00 |
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Eddie Hung
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8aab7fe7e6
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Fix SRL16/32 techmap off-by-one
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2019-02-28 13:56:00 -08:00 |
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Clifford Wolf
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069801e441
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Merge pull request #833 from YosysHQ/clifford/fix831
Fix smt2 code generation for partially initialized memory words, fixe…
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2019-02-28 13:40:27 -08:00 |
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Clifford Wolf
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f570aa5e1d
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Fix smt2 code generation for partially initialized memowy words, fixes #831
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-28 12:15:58 -08:00 |
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Clifford Wolf
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5e94a8a127
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Merge pull request #832 from YosysHQ/supercover
Add "supercover" pass
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2019-02-28 12:08:01 -08:00 |
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Eddie Hung
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fe4d6898de
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synth_xilinx to call shregmap with enable support
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2019-02-28 11:17:13 -08:00 |
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Eddie Hung
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68f38f2ee0
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synth_xilinx to use shregmap with -params too
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2019-02-28 10:21:05 -08:00 |
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