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abc9 -- multiple connections for inouts
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1 changed files with 2 additions and 1 deletions
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@ -898,13 +898,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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conn.first = remap_wire;
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conn.second = signal;
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in_wires++;
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module->connect(conn);
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}
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if (w->port_output) {
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conn.first = signal;
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conn.second = remap_wire;
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out_wires++;
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module->connect(conn);
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}
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module->connect(conn);
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}
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//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
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