Emil J
86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef
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Undefine set&reset behavior of $dffsr
2026-04-08 14:22:34 +00:00
tondapusili
5b22e64d19
sim: cache sigmap in register_output_step_values
2026-03-24 16:10:11 -07:00
tondapusili
69219e6be0
sim: early-return from checkSignals in sim mode
2026-03-20 12:32:49 -07:00
Emil J. Tywoniak
498cb79abe
async2sync: explain dffsr control signal variable polarity
2026-03-09 20:18:56 +01:00
Emil J. Tywoniak
43ef4d2901
fixup! async2sync: $dffsr has undef output on S&R
2026-03-09 20:12:24 +01:00
Emil J. Tywoniak
ecb8b20f62
yosys: use newcelltypes for yosys_celltypes users
2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
6f74c54c02
async2sync: $dffsr has undef output on S&R
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
a53104379d
clk2fflogic: $dffsr has undef output on S&R
2026-03-03 10:34:29 +01:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
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equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Emil J. Tywoniak
77f64de997
satgen: move report_missing_model here from equiv.h
2026-02-16 17:01:09 +01:00
Emil J. Tywoniak
81ea922512
sat: use the same cell import warnings as equiv
2026-02-16 16:54:26 +01:00
Gus Smith
1502e23371
Set solver from scratchpad or command line
2026-02-06 19:26:32 -08:00
Gus Smith
f062a0c8d6
Typo
2026-02-06 17:26:08 -08:00
Emil J. Tywoniak
8e73e2a306
sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency
2026-02-03 18:10:29 +01:00
Krystine Sherwin
5b317ee03c
sim.cc: Check eval err
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Some cells (e.g. $macc_v2) are marked evaluable, but will raise an abort if called with `CellTypes::eval()`.
Instead of falling through to the abort, we can pass a pointer to a boolean to check for errors.
Use said check to catch `CellTypes::eval()` errors and treat them as unevaluable but otherwise continue.
Reflows the series of if checks into `if ... else if ... else` so that we can check for errors and set state in one place.
2025-12-15 12:08:07 +13:00
Jannis Harder
6a0ee6e4fb
Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
Miodrag Milanovic
f11a61b32b
sim: Make cycle width small as possible and configurable
2025-10-16 11:37:44 +02:00
KrystalDelusion
d4071b63f7
Merge pull request #5268 from YosysHQ/krys/cutpoint_inout
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Track wire drivers in cutpoint
2025-09-24 04:14:19 +12:00
Emil J
73e47ac3fe
Merge pull request #5357 from rocallahan/builtin-ff
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Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
2025-09-17 11:37:16 +02:00
Robert O'Callahan
d24488d3a5
Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff()
2025-09-17 03:24:19 +00:00
Robert O'Callahan
a7c46f7b4a
Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()
2025-09-16 23:02:16 +00:00
Robert O'Callahan
5ac6858f26
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
Robert O'Callahan
d1642bf510
Update passes/sat to avoid bits()
2025-09-16 03:17:23 +00:00
Robert O'Callahan
e0ae7b7af4
Remove .c_str() calls from log()/log_error()
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There are some leftovers, but this is an easy regex-based approach that removes most of them.
2025-09-11 20:59:37 +00:00
Robert O'Callahan
d34ac0c87d
Make log() use the FmtString infrastructure.
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Now `log()` supports `std::string`.
We have to fix a few places where the format parameter was not a compile time constant.
This is mostly trivial.
2025-09-09 15:41:03 +02:00
Robert O'Callahan
c7df6954b9
Remove .c_str() from stringf parameters
2025-09-01 23:34:42 +00:00
Krystine Sherwin
4ac100fe13
cutpoint: Track wire drivers
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Necessary to avoid multiple drivers being inserted when a blackbox has inout ports (like when importing an unknown module with `verific`).
If any bits of an inout port have a known driver, treat the port as an input.
If there are no bits with a known driver, treat the port as an output, and mark each bit as having a driver.
2025-08-06 18:11:05 +12:00
Krystine Sherwin
3959d19291
Reapply "Add groups to command reference"
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This reverts commit 81f87ce6ed
2025-08-06 13:52:12 +12:00
N. Engelhardt
81f87ce6ed
Revert "Add groups to command reference"
2025-07-23 14:41:49 +00:00
Krystine Sherwin
4ba403829b
cmdref: Groups and group names
2025-07-21 10:36:19 +12:00
Krystine Sherwin
af3c28f274
synthprop: Use override keyword
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`formatted_help()` introduced the override keyword, which means that the other two methods that were marked as virtual instead raised a warning about inconsistent use of override. This fixes that by bringing the synthprop (more) in line with the rest of the code-base.
2025-07-21 10:36:18 +12:00
Krystine Sherwin
92ab125113
cmdref: Assigning cmds to formal group
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Give formal index a proper title.
Use `Pass::formatted_help()` to assign the group, but still return `false` because the help text still comes from `Pass::help()`.
Tidy up some of the affected files' includes to make use of the shared `yosys.h` includes.
2025-07-21 10:35:56 +12:00
KrystalDelusion
4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst
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Update fstlib
2025-05-16 09:22:52 +12:00
KrystalDelusion
f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole
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cutpoint: Re-add whole module optimization
2025-05-16 09:22:28 +12:00
Krystine Sherwin
d0b9a0cb98
sim.cc: Move cycle check
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Calling `throw dst_end_of_data_exception()` when the desired number of cycles has been reached means that the fst reader can't tidy up after itself and leads to memory leaks.
This doesn't happen when the `-stop` flag is used because the `Yosys::FstData` struct tracks the end time and skips the outer callback if the simulation has gone past the desired end time.
Move cycle checking into the inner callback along with the time checking means that the outer callback no longer needs to throw an exception in order to stop checking further values, while still allowing the fst reader to finish reading and deallocate memory.
2025-05-12 12:48:01 +12:00
Krystine Sherwin
cc402ee065
libs/fst: Update upstream
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libfst is no longer included in gtkwave and instead has its own repo. There has also been some refactoring, so the patches need to update to match, as does sim.cc.
2025-05-12 10:21:06 +12:00
Emil J. Tywoniak
90a2c92370
driver: allow --no-version still write things like Generated by Yosys
2025-05-07 11:34:23 +02:00
Krystine Sherwin
7c89355b70
cutpoint: Re-add whole module optimization
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Also add a test script for it.
2025-05-06 09:57:34 +12:00
Emil J. Tywoniak
d7affb8821
driver: add --no-version to suppress writing Yosys version in command outputs
2025-05-05 13:12:08 +02:00
Jannis Harder
31d6d0ac17
formalff: Fix -declockgate test and missing emit for memories
2025-04-18 18:57:59 +02:00
Jannis Harder
b982da9f6a
formalff: Document -declockgate option
2025-04-18 17:44:39 +02:00
Jannis Harder
bd154a7188
formalff: Add -declockgate option
2025-04-18 17:44:34 +02:00
Krystine Sherwin
87d3b09988
cutpoint.cc: Fold -instances into -blackbox
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Replace `cutpoint -blackbox` behaviour with `cutpoint -blackbox -instances` behaviour.
Drop `-instances` flag.
Add `-noscopeinfo` flag.
Use `RTLIL::Selection::boxed_module()` helper to shortcut blackbox check.
Update `cutpoint_blackbox.ys` tests to match.
2025-04-11 04:12:35 +12:00
Krystine Sherwin
8b1cc6e05e
cutpoint: Use new selection helpers
2025-04-11 04:12:34 +12:00
Krystine Sherwin
b705c546ea
cutpoint: Add -blackbox -instances
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Replace module instances instead of module contents.
This fixes parametrisable width mismatch with read_verilog frontend, but not verific frontend.
2025-04-11 04:12:34 +12:00
Krystine Sherwin
ca57df8927
cutpoint: Add $scopeinfo cell
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Also adds "blackbox" as a valid TYPE.
2025-04-11 04:12:34 +12:00
Krystine Sherwin
583771ef5b
cutpoint: Add -blackbox option
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Replace the contents of all blackboxes in the design with a formal cut point.
Includes test script.
2025-04-11 04:12:34 +12:00
Krystine Sherwin
cd3b914132
Reinstate #4768
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Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Miodrag Milanović
d49364d96f
Revert "Refactor full_selection"
2025-04-07 12:11:55 +02:00
KrystalDelusion
98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections
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Refactor full_selection
2025-04-05 14:15:27 +13:00
