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cutpoint: Add -blackbox option

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Replace the contents of all blackboxes in the design with a formal cut point.
Includes test script.
This commit is contained in:
Krystine Sherwin 2025-04-11 04:12:34 +12:00
parent 3410e10ed5
commit 583771ef5b
No known key found for this signature in database
2 changed files with 58 additions and 2 deletions
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27
passes/sat/cutpoint.cc
View file

@ -37,10 +37,15 @@ struct CutpointPass : public Pass {
log(" set cutpoint nets to undef (x). the default behavior is to create\n");
log(" an $anyseq cell and drive the cutpoint net from that\n");
log("\n");
log(" cutpoint -blackbox [options]\n");
log("\n");
log("Replace the contents of all blackboxes in the design with a formal cut point.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_undef = false;
bool flag_undef = false;
bool flag_blackbox = false;
log_header(design, "Executing CUTPOINT pass.\n");
@ -51,11 +56,25 @@ struct CutpointPass : public Pass {
flag_undef = true;
continue;
}
if (args[argidx] == "-blackbox") {
flag_blackbox = true;
continue;
}
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
if (flag_blackbox) {
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
RTLIL::Selection module_boxes(false);
for (auto module : design->modules())
if (module->get_blackbox_attribute())
module_boxes.select(module);
design->selection_stack.push_back(module_boxes);
}
for (auto module : design->all_selected_modules())
{
if (module->is_selected_whole()) {
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
@ -68,6 +87,10 @@ struct CutpointPass : public Pass {
output_wires.push_back(wire);
for (auto wire : output_wires)
module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire)));
if (module->get_blackbox_attribute()) {
module->set_bool_attribute(ID::blackbox, false);
module->set_bool_attribute(ID::whitebox, false);
}
continue;
}

33
tests/various/cutpoint_blackbox.ys Normal file
View file

@ -0,0 +1,33 @@
read_verilog -specify << EOT
module top(input a, b, output o);
wire c, d;
bb bb1 (.a (a), .b (b), .o (c));
wb wb1 (.a (a), .b (b), .o (d));
some_mod some_inst (.a (c), .b (d), .o (o));
endmodule
(* blackbox *)
module bb(input a, b, output o);
assign o = a | b;
specify
(a => o) = 1;
endspecify
endmodule
(* whitebox *)
module wb(input a, b, output o);
assign o = a ^ b;
endmodule
module some_mod(input a, b, output o);
assign o = a & b;
endmodule
EOT
select top
select -assert-count 0 t:$anyseq
select -assert-count 2 =t:?b
cutpoint -blackbox =*
select -assert-count 2 t:$anyseq
select -assert-count 2 t:?b