nella
6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup
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Add warnings and errors to `sim -r` with VCD code path
2026-06-22 09:02:32 +00:00
Catherine
a727e7f6e7
Migrate build system to CMake
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See #5895 for details.
This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
nella
886d0a7043
Merge branch 'main' into gus/sim-with-vcd-tuneup
2026-05-19 12:17:29 +02:00
nella
44a1abdade
Don't repeat VCD warnings + fixups.
2026-05-19 12:16:29 +02:00
Miodrag Milanovic
75dcbe03c6
Convert RTLIL::unescape_id of IdString to unescape()
2026-05-16 19:49:45 +02:00
Miodrag Milanovic
8bbc3c359c
Remove id2cstr uses in our code base
2026-05-16 19:49:45 +02:00
Miodrag Milanović
1d87cefd80
Merge pull request #5882 from YosysHQ/std_cpp20
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Bump required standard to C++20
2026-05-15 13:13:43 +00:00
Miodrag Milanović
36eceed720
Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id
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Cleaning up log_id()
2026-05-15 11:07:43 +00:00
Miodrag Milanovic
90e019e319
Fix compiling on GCC11
2026-05-13 10:11:36 +02:00
Emil J. Tywoniak
3a150f2883
remove unused hashlib containers
2026-05-12 12:52:10 +02:00
Codexplorer
e41b969da2
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
Scott Ashcroft
23a05fcf35
Add comments to make sure it is clear scale is an exponent of 10
2026-04-23 17:22:14 +01:00
Scott Ashcroft
e69341cd5f
Make sure co-simulation only uses integer arithmetic
2026-04-23 17:22:14 +01:00
Emil J
86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef
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Undefine set&reset behavior of $dffsr
2026-04-08 14:22:34 +00:00
tondapusili
5b22e64d19
sim: cache sigmap in register_output_step_values
2026-03-24 16:10:11 -07:00
tondapusili
69219e6be0
sim: early-return from checkSignals in sim mode
2026-03-20 12:32:49 -07:00
Emil J. Tywoniak
498cb79abe
async2sync: explain dffsr control signal variable polarity
2026-03-09 20:18:56 +01:00
Emil J. Tywoniak
43ef4d2901
fixup! async2sync: $dffsr has undef output on S&R
2026-03-09 20:12:24 +01:00
Emil J. Tywoniak
ecb8b20f62
yosys: use newcelltypes for yosys_celltypes users
2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
6f74c54c02
async2sync: $dffsr has undef output on S&R
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
a53104379d
clk2fflogic: $dffsr has undef output on S&R
2026-03-03 10:34:29 +01:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
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equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Gus Smith
366f98ae25
ADd clarification
2026-02-23 11:51:54 -08:00
Gus Smith
b454582f54
Detect undriven and error/warn
2026-02-20 11:00:59 -08:00
Gus Smith
cdc728b6f0
Suggest use of YW when possible
2026-02-20 09:33:51 -08:00
Emil J. Tywoniak
77f64de997
satgen: move report_missing_model here from equiv.h
2026-02-16 17:01:09 +01:00
Emil J. Tywoniak
81ea922512
sat: use the same cell import warnings as equiv
2026-02-16 16:54:26 +01:00
Gus Smith
1502e23371
Set solver from scratchpad or command line
2026-02-06 19:26:32 -08:00
Gus Smith
f062a0c8d6
Typo
2026-02-06 17:26:08 -08:00
Emil J. Tywoniak
8e73e2a306
sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency
2026-02-03 18:10:29 +01:00
Krystine Sherwin
5b317ee03c
sim.cc: Check eval err
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Some cells (e.g. $macc_v2) are marked evaluable, but will raise an abort if called with `CellTypes::eval()`.
Instead of falling through to the abort, we can pass a pointer to a boolean to check for errors.
Use said check to catch `CellTypes::eval()` errors and treat them as unevaluable but otherwise continue.
Reflows the series of if checks into `if ... else if ... else` so that we can check for errors and set state in one place.
2025-12-15 12:08:07 +13:00
Jannis Harder
6a0ee6e4fb
Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
Miodrag Milanovic
f11a61b32b
sim: Make cycle width small as possible and configurable
2025-10-16 11:37:44 +02:00
KrystalDelusion
d4071b63f7
Merge pull request #5268 from YosysHQ/krys/cutpoint_inout
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Track wire drivers in cutpoint
2025-09-24 04:14:19 +12:00
Emil J
73e47ac3fe
Merge pull request #5357 from rocallahan/builtin-ff
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Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
2025-09-17 11:37:16 +02:00
Robert O'Callahan
d24488d3a5
Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff()
2025-09-17 03:24:19 +00:00
Robert O'Callahan
a7c46f7b4a
Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()
2025-09-16 23:02:16 +00:00
Robert O'Callahan
5ac6858f26
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
Robert O'Callahan
d1642bf510
Update passes/sat to avoid bits()
2025-09-16 03:17:23 +00:00
Robert O'Callahan
e0ae7b7af4
Remove .c_str() calls from log()/log_error()
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There are some leftovers, but this is an easy regex-based approach that removes most of them.
2025-09-11 20:59:37 +00:00
Robert O'Callahan
d34ac0c87d
Make log() use the FmtString infrastructure.
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Now `log()` supports `std::string`.
We have to fix a few places where the format parameter was not a compile time constant.
This is mostly trivial.
2025-09-09 15:41:03 +02:00
Robert O'Callahan
c7df6954b9
Remove .c_str() from stringf parameters
2025-09-01 23:34:42 +00:00
Krystine Sherwin
4ac100fe13
cutpoint: Track wire drivers
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Necessary to avoid multiple drivers being inserted when a blackbox has inout ports (like when importing an unknown module with `verific`).
If any bits of an inout port have a known driver, treat the port as an input.
If there are no bits with a known driver, treat the port as an output, and mark each bit as having a driver.
2025-08-06 18:11:05 +12:00
Krystine Sherwin
3959d19291
Reapply "Add groups to command reference"
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This reverts commit 81f87ce6ed
2025-08-06 13:52:12 +12:00
N. Engelhardt
81f87ce6ed
Revert "Add groups to command reference"
2025-07-23 14:41:49 +00:00
Krystine Sherwin
4ba403829b
cmdref: Groups and group names
2025-07-21 10:36:19 +12:00
Krystine Sherwin
af3c28f274
synthprop: Use override keyword
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`formatted_help()` introduced the override keyword, which means that the other two methods that were marked as virtual instead raised a warning about inconsistent use of override. This fixes that by bringing the synthprop (more) in line with the rest of the code-base.
2025-07-21 10:36:18 +12:00
Krystine Sherwin
92ab125113
cmdref: Assigning cmds to formal group
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Give formal index a proper title.
Use `Pass::formatted_help()` to assign the group, but still return `false` because the help text still comes from `Pass::help()`.
Tidy up some of the affected files' includes to make use of the shared `yosys.h` includes.
2025-07-21 10:35:56 +12:00
KrystalDelusion
4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst
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Update fstlib
2025-05-16 09:22:52 +12:00
KrystalDelusion
f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole
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cutpoint: Re-add whole module optimization
2025-05-16 09:22:28 +12:00
