mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 11:45:41 +00:00
Code Activity
17376 commits 135 branches 69 tags 58 MiB
Commit graph

552 commits

Author SHA1 Message Date
Emil J. Tywoniak
7c73fd62e4 twine: fix replayability, reduce TwineSearch usage 2026-06-22 17:53:19 +02:00
Emil J. Tywoniak
ef4ed3ef15 twine: auto type WIP 2026-06-22 00:29:11 +02:00
Emil J. Tywoniak
54a3baa2de rtlil: fix twine handling 2026-06-19 11:39:47 +02:00
Emil J. Tywoniak
bffe7a6e57 WIP migration to twine 2026-06-18 21:54:57 +02:00
Emil J. Tywoniak
0c450ce8c8 WIP migration to twine 2026-06-18 19:27:41 +02:00
Emil J. Tywoniak
3a5f5c77bf twine: avoid TwinePool::lookup 2026-06-16 22:57:13 +02:00
Emil J. Tywoniak
45c1654938 twine: GC again WIP 2026-06-16 13:15:39 +02:00
Emil J. Tywoniak
9cb838febe twine: fix another off-by-one 2026-06-15 18:55:21 +02:00
Emil J. Tywoniak
d96461e40c twine: fix off-by-one static twine error 2026-06-15 17:41:21 +02:00
Emil J. Tywoniak
dcc74755e7 WIP 2026-06-15 11:26:09 +02:00
Emil J. Tywoniak
d22805bd47 WIP 2026-06-12 16:25:07 +02:00
Emil J. Tywoniak
c3ffbf6fae WIP 2026-06-12 00:18:53 +02:00
Emil J. Tywoniak
afdae7b87e WIP 2026-06-11 20:02:02 +02:00
Emil J. Tywoniak
8e522b08c0 WIP 2026-06-11 13:17:54 +02:00
Emil J. Tywoniak
f592f2f3af WIP 2026-06-10 19:22:53 +02:00
Emil J. Tywoniak
2117af318c WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
d13dfc21f4 WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
1a8a95b472 rtlil: fix masquerade 2026-06-10 14:54:45 +02:00
Emil J. Tywoniak
2d3b7e9c92 rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge) 2026-06-10 14:54:43 +02:00
Emil J. Tywoniak
734593e12d rtlil: Module::clone attaches to source design; callers use clone(dst) 2026-06-10 14:54:34 +02:00
Emil J. Tywoniak
8f8a07efee rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer 2026-06-10 14:54:31 +02:00
Emil J. Tywoniak
0f31d3089e rtlil: extend per-Design meta vector to hold name slot 2026-06-10 14:54:16 +02:00
Emil J. Tywoniak
f1edb571f2 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
Emil J. Tywoniak
e70eed3296 rtlil: add Module* back-pointer to RTLIL::Memory 2026-06-10 14:53:59 +02:00
Emil J. Tywoniak
9ed93e210b rtlil: add per-Design src meta vector + freelist 2026-06-10 14:53:55 +02:00
Emil J. Tywoniak
29ab42bc4e rtlil: add Module* back-pointer to inner-process AttrObjects 2026-06-10 14:53:48 +02:00
Emil J. Tywoniak
3424c00cd0 twine 2026-06-10 14:53:45 +02:00
Emil J. Tywoniak
c3457e2e5c WIP 2026-06-10 14:52:50 +02:00
Emil J. Tywoniak
9f22b9d2a0 patch: source transfer 2026-05-23 00:10:02 +02:00
Emil J. Tywoniak
e78e19acfe patch: fix patch mixins 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak
dbc7e33908 rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch 2026-05-23 00:09:14 +02:00
Emil J. Tywoniak
3e6b740430 rtlil: allow friends to use Cell constructors with a factory token pattern 2026-05-23 00:07:39 +02:00
Emil J. Tywoniak
7905df89f3 rtlil: fix cloneInto in signorm 2026-05-22 18:40:01 +02:00
Emil J. Tywoniak
754709aa01 rtlil: sigNormalize Module when added to Design in signorm mode 2026-05-22 18:40:00 +02:00
Jannis Harder
423c8be71b WIP half broken snapshot 2026-05-22 18:37:11 +02:00
Miodrag Milanovic
8bbc3c359c Remove id2cstr uses in our code base 2026-05-16 19:49:45 +02:00
Codexplorer
e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Emil J. Tywoniak
25b9b796c4 rtlil: complicate extract again for packing 2026-04-24 11:04:19 +02:00
Emil J. Tywoniak
14b0efeced rtlil: simplify extract for performance 2026-04-23 13:58:20 +02:00
Emil J. Tywoniak
ea11453cef rtlil: faster remove2 2026-03-18 23:33:35 +01:00
Robert O'Callahan
b42bb05b63 Parallelize Design::check() 2026-03-06 02:03:21 +00:00
Robert O'Callahan
e2166c4684 Parallelize collect_garbage() 2026-03-06 02:03:21 +00:00
nella
04822c6660 Readd builtin_ff_cell_types for plugin parity. 2026-03-04 12:39:45 +01:00
nella
66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
3212dfaf1f newcelltypes: fix unit test 2026-03-04 12:22:14 +01:00
Robert O'Callahan
dcd7742d52 Avoid scanning entire module if there are no wires to remove 
It's pretty common for `opt_clean` to find no wires to remove. In that case,
there is no point scanning the entire design, which can be significantly
expensive for huge designs.
 2026-01-23 01:38:20 +00:00
Robert O'Callahan
2c0448a81b Avoid spurious copy in IdStringCollector::trace_named() 2026-01-21 03:31:56 +00:00
nella
210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
Emil J
0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00