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Code Activity
12578 commits 122 branches 59 tags 72 MiB
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2195 commits

Author SHA1 Message Date
Clifford Wolf
d2d402e625 Run "peepopt" in generic "synth" pass and "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 08:10:37 +02:00
Eddie Hung
e97178a888 WIP 2019-04-28 12:51:00 -07:00
Eddie Hung
af840bbc63 Move neg-pol to pos-pol mapping from ff_map to cells_map.v 2019-04-28 12:36:04 -07:00
Eddie Hung
4aca928033 Fix spacing 2019-04-26 19:46:34 -07:00
Eddie Hung
d855683917 Revert synth_xilinx 'fine' label more to how it used to be... 2019-04-26 16:53:16 -07:00
Eddie Hung
ccc283737d Apparently, this reduces number of MUXCY/XORCY 2019-04-26 16:28:48 -07:00
Eddie Hung
e31e21766d Try a different approach with 'muxcover' 2019-04-26 16:09:54 -07:00
Eddie Hung
76b7c5d4cc Merge remote-tracking branch 'origin/master' into xc7mux 2019-04-26 15:35:55 -07:00
Eddie Hung
ea0e0722bb Where did this check come from!?! 2019-04-26 15:35:34 -07:00
Eddie Hung
6b9ca7cd6d Remove split_shiftx call 2019-04-26 15:32:58 -07:00
Eddie Hung
8469d9fe9f Missing newline 2019-04-26 14:51:37 -07:00
Eddie Hung
727eec04c5 Refactor synth_xilinx to auto-generate doc 2019-04-26 14:32:18 -07:00
Eddie Hung
1ea6d7920f Cleanup ice40 2019-04-26 14:31:59 -07:00
Eddie Hung
f14d7f0df6 Cleanup superseded 2019-04-25 19:43:41 -07:00
Eddie Hung
019c48b508 bitblast_shiftx -> split_shiftx 2019-04-25 19:38:35 -07:00
Eddie Hung
feff976454 synth_xilinx to call bitblast_shiftx 2019-04-25 17:11:18 -07:00
Eddie Hung
f96d82a5f1 Add -nocarry option to synth_xilinx 2019-04-24 16:46:41 -07:00
Clifford Wolf
64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00
Eddie Hung
91c3afcab7 Use nonblocking 2019-04-23 13:42:06 -07:00
Clifford Wolf
4575e4ad86 Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
a7e11261bd Add $specify2 and $specify3 cells to simlib 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Eddie Hung
0bd2bfa737 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 18:15:28 -07:00
Eddie Hung
60026842b2 Tweak 2019-04-22 17:59:56 -07:00
Eddie Hung
26e461f47d Fix for A_WIDTH == 2 but B_WIDTH==3 2019-04-22 17:58:28 -07:00
Eddie Hung
1fa2c36fbd Trim A_WIDTH by Y_WIDTH-1 2019-04-22 17:14:11 -07:00
Eddie Hung
69863f7698 Add comment 2019-04-22 16:58:44 -07:00
Eddie Hung
61161faefc Fix for mux_case_* mappings 2019-04-22 16:56:18 -07:00
Eddie Hung
ac1e13819e Fix for non-pow2 width muxes 2019-04-22 14:26:13 -07:00
Eddie Hung
75b96b1aff Add synth_xilinx -nomux option 2019-04-22 12:36:15 -07:00
Eddie Hung
79fb291dbe Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
Eddie Hung
4cfef7897f Merge branch 'xaig' into xc7mux 2019-04-22 11:58:59 -07:00
Eddie Hung
4486a98fd5 Merge remote-tracking branch 'origin/xc7srl' into xc7mux 2019-04-22 11:45:49 -07:00
Eddie Hung
ec88129a5c Update help message 2019-04-22 11:38:23 -07:00
Eddie Hung
4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Eddie Hung
0e76718720 Move 'shregmap -tech xilinx' into map_cells 2019-04-22 10:45:39 -07:00
Eddie Hung
e300b1922c Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-22 10:36:27 -07:00
Clifford Wolf
0e7901e45c
Merge pull request #941 from Wren6991/sim_lib_io_clke 
ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
 2019-04-22 09:11:13 +02:00
Clifford Wolf
913659d644 Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
Clifford Wolf
cf1ba46fa0 Re-added clean after techmap in synth_xilinx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 09:03:11 +02:00
Clifford Wolf
cbd9b8a3f3
Merge pull request #916 from YosysHQ/map_cells_before_map_luts 
synth_xilinx to map_cells before map_luts
 2019-04-22 09:01:00 +02:00
Clifford Wolf
19fd411e77
Merge pull request #911 from mmicko/gowin-nobram 
Make nobram false by default for gowin
 2019-04-22 08:58:09 +02:00
Eddie Hung
d342b5b135 Tidy up, fix for -nosrl 2019-04-21 15:33:03 -07:00
Eddie Hung
d7f0700bae Convert to use #945 2019-04-21 15:19:02 -07:00
Eddie Hung
726e2da8f2 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-21 14:28:55 -07:00
Eddie Hung
a3371e118b Merge branch 'master' into map_cells_before_map_luts 2019-04-21 14:24:50 -07:00
Eddie Hung
ae95aba60a Add comments 2019-04-21 14:16:59 -07:00
Eddie Hung
d99422411f Use new pmux2shiftx from #944, remove my old attempt 2019-04-21 14:16:34 -07:00
Luke Wren
71da836300 ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments 2019-04-21 21:40:11 +01:00