3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00

Improve $specrule interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-23 22:18:04 +02:00
parent 71c38d9de5
commit 4575e4ad86
3 changed files with 24 additions and 24 deletions

View file

@ -1419,6 +1419,10 @@ endmodule
module \$specrule (EN_SRC, EN_DST, SRC, DST);
parameter SKEW = 0;
parameter HOLD = 0;
parameter T_LIMIT = 0;
parameter SRC_WIDTH = 1;
parameter DST_WIDTH = 1;
@ -1428,9 +1432,6 @@ parameter SRC_POL = 0;
parameter DST_PEN = 0;
parameter DST_POL = 0;
parameter LIMIT_GT = 0;
parameter T_LIMIT = 0;
input EN_SRC, EN_DST;
input [SRC_WIDTH-1:0] SRC;
input [DST_WIDTH-1:0] DST;