Clifford Wolf cbd9b8a3f3 Merge pull request #916 from YosysHQ/map_cells_before_map_luts ... synth_xilinx to map_cells before map_luts		2019-04-22 09:01:00 +02:00
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achronix	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
anlogic	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
common	Merge pull request #772 from whitequark/synth_lut	2019-01-02 15:44:57 +01:00
coolrunner2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
gowin	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
greenpak4	techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module	2019-02-26 09:40:46 -08:00
ice40	Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes	2019-03-12 20:14:18 +01:00
intel	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
sf2	Add link to SF2 / igloo2 macro library guide	2019-03-07 09:08:26 -08:00
xilinx	Merge branch 'master' into map_cells_before_map_luts	2019-04-21 14:24:50 -07:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00