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yosys/techlibs
Clifford Wolf cbd9b8a3f3
Merge pull request #916 from YosysHQ/map_cells_before_map_luts
synth_xilinx to map_cells before map_luts
2019-04-22 09:01:00 +02:00
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achronix Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
anlogic Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
common Merge pull request #772 from whitequark/synth_lut 2019-01-02 15:44:57 +01:00
coolrunner2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
easic Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ecp5 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
gowin Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
greenpak4 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ice40 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
intel Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
sf2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
xilinx Merge branch 'master' into map_cells_before_map_luts 2019-04-21 14:24:50 -07:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00