mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
This commit is contained in:
Eddie Hung
commit
4486a98fd5
77 changed files with 4701 additions and 347 deletions
|
|
@ -1,7 +1,17 @@
|
|||
|
||||
OBJS += techlibs/gowin/synth_gowin.o
|
||||
OBJS += techlibs/gowin/determine_init.o
|
||||
|
||||
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/bram.txt))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/drams_map.v))
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt))
|
||||
|
||||
|
||||
|
||||
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh))
|
||||
|
||||
|
|
|
|||
29
techlibs/gowin/bram.txt
Normal file
29
techlibs/gowin/bram.txt
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
bram $__GW1NR_SDP
|
||||
# uncomment when done
|
||||
# init 1
|
||||
abits 10 @a10d18
|
||||
dbits 16 @a10d18
|
||||
abits 11 @a11d9
|
||||
dbits 8 @a11d9
|
||||
abits 12 @a12d4
|
||||
dbits 4 @a12d4
|
||||
abits 13 @a13d2
|
||||
dbits 2 @a13d2
|
||||
abits 14 @a14d1
|
||||
dbits 1 @a14d1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 1 0
|
||||
enable 1 1 @a10d18
|
||||
enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
match $__GW1NR_SDP
|
||||
min bits 2048
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
12
techlibs/gowin/brams_init3.vh
Normal file
12
techlibs/gowin/brams_init3.vh
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
localparam [15:0] INIT_0 = {
|
||||
INIT[ 60], INIT[ 56], INIT[ 52], INIT[ 48], INIT[ 44], INIT[ 40], INIT[ 36], INIT[ 32], INIT[ 28], INIT[ 24], INIT[ 20], INIT[ 16], INIT[ 12], INIT[ 8], INIT[ 4], INIT[ 0]
|
||||
};
|
||||
localparam [15:0] INIT_1 = {
|
||||
INIT[ 61], INIT[ 57], INIT[ 53], INIT[ 49], INIT[ 45], INIT[ 41], INIT[ 37], INIT[ 33], INIT[ 29], INIT[ 25], INIT[ 21], INIT[ 17], INIT[ 13], INIT[ 9], INIT[ 5], INIT[ 1]
|
||||
};
|
||||
localparam [15:0] INIT_2 = {
|
||||
INIT[ 62], INIT[ 58], INIT[ 54], INIT[ 50], INIT[ 46], INIT[ 42], INIT[ 38], INIT[ 34], INIT[ 30], INIT[ 26], INIT[ 22], INIT[ 18], INIT[ 14], INIT[ 10], INIT[ 6], INIT[ 2]
|
||||
};
|
||||
localparam [15:0] INIT_3 = {
|
||||
INIT[ 63], INIT[ 59], INIT[ 55], INIT[ 51], INIT[ 47], INIT[ 43], INIT[ 39], INIT[ 35], INIT[ 31], INIT[ 27], INIT[ 23], INIT[ 19], INIT[ 15], INIT[ 11], INIT[ 7], INIT[ 3]
|
||||
};
|
||||
103
techlibs/gowin/brams_map.v
Normal file
103
techlibs/gowin/brams_map.v
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/* Semi Dual Port (SDP) memory have the following configurations:
|
||||
* Memory Config RAM(BIT) Port Mode Memory Depth Data Depth
|
||||
* ----------------|---------| ----------|--------------|------------|
|
||||
* B-SRAM_16K_SD1 16K 16Kx1 16,384 1
|
||||
* B-SRAM_8K_SD2 16K 8Kx2 8,192 2
|
||||
* B-SRAM_4K_SD4 16K 4Kx2 4,096 4
|
||||
*/
|
||||
module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 16;
|
||||
parameter CFG_ENABLE_A = 3;
|
||||
|
||||
parameter [16383:0] INIT = 16384'hx;
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
input [CFG_DBITS-1:0] A1DATA;
|
||||
input [CFG_ENABLE_A-1:0] A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
output [CFG_DBITS-1:0] B1DATA;
|
||||
input B1EN;
|
||||
|
||||
|
||||
generate if (CFG_DBITS == 1) begin
|
||||
SDP #(
|
||||
.READ_MODE(0),
|
||||
.BIT_WIDTH_0(1),
|
||||
.BIT_WIDTH_1(1),
|
||||
.BLK_SEL(3'b000),
|
||||
.RESET_MODE("SYNC")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.CLKA(CLK2), .CLKB(CLK3),
|
||||
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
|
||||
.WREB(1'b0), .CEB(B1EN),
|
||||
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
|
||||
.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
|
||||
);
|
||||
end else if (CFG_DBITS == 2) begin
|
||||
SDP #(
|
||||
.READ_MODE(0),
|
||||
.BIT_WIDTH_0(2),
|
||||
.BIT_WIDTH_1(2),
|
||||
.BLK_SEL(3'b000),
|
||||
.RESET_MODE("SYNC")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.CLKA(CLK2), .CLKB(CLK3),
|
||||
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
|
||||
.WREB(1'b0), .CEB(B1EN),
|
||||
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
|
||||
.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
|
||||
);
|
||||
end else if (CFG_DBITS <= 4) begin
|
||||
SDP #(
|
||||
.READ_MODE(0),
|
||||
.BIT_WIDTH_0(4),
|
||||
.BIT_WIDTH_1(4),
|
||||
.BLK_SEL(3'b000),
|
||||
.RESET_MODE("SYNC")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.CLKA(CLK2), .CLKB(CLK3),
|
||||
.WREA(A1EN), .OCE(1'b0),
|
||||
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
|
||||
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
|
||||
.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
|
||||
);
|
||||
end else if (CFG_DBITS <= 8) begin
|
||||
SDP #(
|
||||
.READ_MODE(0),
|
||||
.BIT_WIDTH_0(8),
|
||||
.BIT_WIDTH_1(8),
|
||||
.BLK_SEL(3'b000),
|
||||
.RESET_MODE("SYNC")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.CLKA(CLK2), .CLKB(CLK3),
|
||||
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
|
||||
.WREB(1'b0), .CEB(B1EN),
|
||||
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
|
||||
.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
|
||||
);
|
||||
end else if (CFG_DBITS <= 16) begin
|
||||
SDP #(
|
||||
.READ_MODE(0),
|
||||
.BIT_WIDTH_0(16),
|
||||
.BIT_WIDTH_1(16),
|
||||
.BLK_SEL(3'b000),
|
||||
.RESET_MODE("SYNC")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.CLKA(CLK2), .CLKB(CLK3),
|
||||
.WREA(A1EN), .OCE(1'b0),
|
||||
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
|
||||
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
|
||||
.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
|
||||
);
|
||||
end else begin
|
||||
wire TECHMAP_FAIL = 1'b1;
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,5 +1,9 @@
|
|||
module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
|
||||
module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
|
||||
module \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
|
||||
|
||||
module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
|
||||
module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
|
||||
module \$__DFFS_PP1_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
|
||||
|
||||
module \$lut (A, Y);
|
||||
parameter WIDTH = 0;
|
||||
|
|
|
|||
|
|
@ -38,6 +38,17 @@ module DFFN (output reg Q, input CLK, D);
|
|||
Q <= D;
|
||||
endmodule
|
||||
|
||||
module DFFR (output reg Q, input D, CLK, RESET);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q = INIT;
|
||||
always @(posedge CLK) begin
|
||||
if (RESET)
|
||||
Q <= 1'b0;
|
||||
else
|
||||
Q <= D;
|
||||
end
|
||||
endmodule // DFFR (positive clock edge; synchronous reset)
|
||||
|
||||
module VCC(output V);
|
||||
assign V = 1;
|
||||
endmodule
|
||||
|
|
@ -63,3 +74,126 @@ module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
|
|||
assign {COUT, SUM} = CIN + I1 + I0;
|
||||
endmodule // alu
|
||||
|
||||
module RAM16S4 (DO, DI, AD, WRE, CLK);
|
||||
parameter WIDTH = 4;
|
||||
parameter INIT_0 = 16'h0000;
|
||||
parameter INIT_1 = 16'h0000;
|
||||
parameter INIT_2 = 16'h0000;
|
||||
parameter INIT_3 = 16'h0000;
|
||||
|
||||
input [WIDTH-1:0] AD;
|
||||
input [WIDTH-1:0] DI;
|
||||
output [WIDTH-1:0] DO;
|
||||
input CLK;
|
||||
input WRE;
|
||||
|
||||
reg [15:0] mem0, mem1, mem2, mem3;
|
||||
|
||||
initial begin
|
||||
mem0 = INIT_0;
|
||||
mem1 = INIT_1;
|
||||
mem2 = INIT_2;
|
||||
mem3 = INIT_3;
|
||||
end
|
||||
|
||||
assign DO[0] = mem0[AD];
|
||||
assign DO[1] = mem1[AD];
|
||||
assign DO[2] = mem2[AD];
|
||||
assign DO[3] = mem3[AD];
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (WRE) begin
|
||||
mem0[AD] <= DI[0];
|
||||
mem1[AD] <= DI[1];
|
||||
mem2[AD] <= DI[2];
|
||||
mem3[AD] <= DI[3];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // RAM16S4
|
||||
|
||||
|
||||
(* blackbox *)
|
||||
module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
|
||||
//1'b0: Bypass mode; 1'b1 Pipeline mode
|
||||
parameter READ_MODE = 1'b0;
|
||||
parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32
|
||||
parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32
|
||||
parameter BLK_SEL = 3'b000;
|
||||
parameter RESET_MODE = "SYNC";
|
||||
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
input CLKA, CEA, CLKB, CEB;
|
||||
input OCE; // clock enable of memory output register
|
||||
input RESETA, RESETB; // resets output registers, not memory contents
|
||||
input WREA, WREB; // 1'b0: read enabled; 1'b1: write enabled
|
||||
input [13:0] ADA, ADB;
|
||||
input [31:0] DI;
|
||||
input [2:0] BLKSEL;
|
||||
output [31:0] DO;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
72
techlibs/gowin/determine_init.cc
Normal file
72
techlibs/gowin/determine_init.cc
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/sigtools.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct DetermineInitPass : public Pass {
|
||||
DetermineInitPass() : Pass("determine_init", "Determine the init value of cells") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
log("\n");
|
||||
log(" determine_init [selection]\n");
|
||||
log("\n");
|
||||
log("Determine the init value of cells that doesn't allow unknown init value.\n");
|
||||
log("\n");
|
||||
}
|
||||
|
||||
Const determine_init(Const init)
|
||||
{
|
||||
for (int i = 0; i < GetSize(init); i++) {
|
||||
if (init[i] != State::S0 && init[i] != State::S1)
|
||||
init[i] = State::S0;
|
||||
}
|
||||
|
||||
return init;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
log_header(design, "Executing DETERMINE_INIT pass (determine init value for cells).\n");
|
||||
|
||||
extra_args(args, args.size(), design);
|
||||
|
||||
size_t cnt = 0;
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type == "\\RAM16S4")
|
||||
{
|
||||
cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0")));
|
||||
cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1")));
|
||||
cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2")));
|
||||
cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3")));
|
||||
cnt++;
|
||||
}
|
||||
}
|
||||
}
|
||||
log_header(design, "Updated %lu cells with determined init value.\n", cnt);
|
||||
}
|
||||
} DetermineInitPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
17
techlibs/gowin/dram.txt
Normal file
17
techlibs/gowin/dram.txt
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
bram $__GW1NR_RAM16S4
|
||||
init 1
|
||||
abits 4
|
||||
dbits 4
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 1
|
||||
clocks 0 1
|
||||
clkpol 0 1
|
||||
endbram
|
||||
|
||||
match $__GW1NR_RAM16S4
|
||||
make_outreg
|
||||
min wports 1
|
||||
endmatch
|
||||
31
techlibs/gowin/drams_map.v
Normal file
31
techlibs/gowin/drams_map.v
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 4;
|
||||
parameter CFG_DBITS = 4;
|
||||
|
||||
parameter [63:0] INIT = 64'bx;
|
||||
input CLK1;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input B1EN;
|
||||
|
||||
`include "brams_init3.vh"
|
||||
|
||||
RAM16S4
|
||||
#(.INIT_0(INIT_0),
|
||||
.INIT_1(INIT_1),
|
||||
.INIT_2(INIT_2),
|
||||
.INIT_3(INIT_3))
|
||||
_TECHMAP_REPLACE_
|
||||
(.AD(B1ADDR),
|
||||
.DI(B1DATA),
|
||||
.DO(A1DATA),
|
||||
.CLK(CLK1),
|
||||
.WRE(B1EN));
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -49,9 +49,15 @@ struct SynthGowinPass : public ScriptPass
|
|||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -nodffe\n");
|
||||
log(" do not use flipflops with CE in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" do not use BRAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nodram\n");
|
||||
log(" do not use distributed RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -noflatten\n");
|
||||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
|
|
@ -65,7 +71,7 @@ struct SynthGowinPass : public ScriptPass
|
|||
}
|
||||
|
||||
string top_opt, vout_file;
|
||||
bool retime, flatten, nobram;
|
||||
bool retime, nobram, nodram, flatten, nodffe;
|
||||
|
||||
void clear_flags() YS_OVERRIDE
|
||||
{
|
||||
|
|
@ -73,7 +79,9 @@ struct SynthGowinPass : public ScriptPass
|
|||
vout_file = "";
|
||||
retime = false;
|
||||
flatten = true;
|
||||
nobram = true;
|
||||
nobram = false;
|
||||
nodffe = false;
|
||||
nodram = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
|
|
@ -108,6 +116,14 @@ struct SynthGowinPass : public ScriptPass
|
|||
nobram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodram") {
|
||||
nodram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nodffe") {
|
||||
nodffe = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noflatten") {
|
||||
flatten = false;
|
||||
continue;
|
||||
|
|
@ -147,25 +163,43 @@ struct SynthGowinPass : public ScriptPass
|
|||
{
|
||||
run("synth -run coarse");
|
||||
}
|
||||
if (!nobram && check_label("bram", "(skip if -nobram)"))
|
||||
|
||||
if (!nobram && check_label("bram", "(skip if -nobram)"))
|
||||
{
|
||||
run("memory_bram -rules +/gowin/bram.txt");
|
||||
run("techmap -map +/gowin/brams_map.v");
|
||||
run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
|
||||
}
|
||||
|
||||
if (!nodram && check_label("dram", "(skip if -nodram)"))
|
||||
{
|
||||
run("memory_bram -rules +/gowin/dram.txt");
|
||||
run("techmap -map +/gowin/drams_map.v");
|
||||
run("determine_init");
|
||||
}
|
||||
|
||||
if (check_label("fine"))
|
||||
{
|
||||
run("opt -fast -mux_undef -undriven -fine");
|
||||
run("memory_map");
|
||||
run("opt -undriven -fine");
|
||||
run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
|
||||
run("opt -fine");
|
||||
run("clean -purge");
|
||||
run("splitnets -ports");
|
||||
run("setundef -undriven -zero");
|
||||
run("techmap -map +/techmap.v");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff", "(only if -retime)");
|
||||
}
|
||||
|
||||
if (check_label("map_ffs"))
|
||||
{
|
||||
run("dffsr2dff");
|
||||
run("dff2dffs");
|
||||
run("opt_clean");
|
||||
if (!nodffe)
|
||||
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
|
||||
run("techmap -map +/gowin/cells_map.v");
|
||||
run("opt_expr -mux_undef");
|
||||
run("simplemap");
|
||||
}
|
||||
|
||||
if (check_label("map_luts"))
|
||||
{
|
||||
run("abc -lut 4");
|
||||
|
|
@ -176,8 +210,10 @@ struct SynthGowinPass : public ScriptPass
|
|||
{
|
||||
run("techmap -map +/gowin/cells_map.v");
|
||||
run("hilomap -hicell VCC V -locell GND G");
|
||||
run("iopadmap -inpad IBUF O:I -outpad OBUF I:O");
|
||||
run("clean -purge");
|
||||
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
|
||||
run("dffinit -ff DFF Q INIT");
|
||||
run("clean");
|
||||
|
||||
}
|
||||
|
||||
if (check_label("check"))
|
||||
|
|
|
|||
|
|
@ -27,18 +27,27 @@ module SB_IO (
|
|||
reg dout_q_0, dout_q_1;
|
||||
reg outena_q;
|
||||
|
||||
// IO tile generates a constant 1'b1 internally if global_cen is not connected
|
||||
wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
|
||||
reg clken_pulled_ri;
|
||||
reg clken_pulled_ro;
|
||||
|
||||
generate if (!NEG_TRIGGER) begin
|
||||
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
|
||||
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
|
||||
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
|
||||
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
|
||||
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
|
||||
always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
|
||||
always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
|
||||
always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
|
||||
always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
|
||||
always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
|
||||
always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
|
||||
always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
|
||||
end else begin
|
||||
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
|
||||
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
|
||||
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
|
||||
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
|
||||
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
|
||||
always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
|
||||
always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
|
||||
always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
|
||||
always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
|
||||
always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
|
||||
always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
|
||||
always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
|
||||
end endgenerate
|
||||
|
||||
always @* begin
|
||||
|
|
|
|||
|
|
@ -17,6 +17,131 @@
|
|||
*
|
||||
*/
|
||||
|
||||
module \$__SHREG_ (input C, input D, input E, output Q);
|
||||
parameter DEPTH = 0;
|
||||
parameter [DEPTH-1:0] INIT = 0;
|
||||
parameter CLKPOL = 1;
|
||||
parameter ENPOL = 2;
|
||||
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
|
||||
endmodule
|
||||
|
||||
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
|
||||
parameter DEPTH = 0;
|
||||
parameter [DEPTH-1:0] INIT = 0;
|
||||
parameter CLKPOL = 1;
|
||||
parameter ENPOL = 2;
|
||||
|
||||
// shregmap's INIT parameter shifts out LSB first;
|
||||
// however Xilinx expects MSB first
|
||||
function [DEPTH-1:0] brev;
|
||||
input [DEPTH-1:0] din;
|
||||
integer i;
|
||||
begin
|
||||
for (i = 0; i < DEPTH; i=i+1)
|
||||
brev[i] = din[DEPTH-1-i];
|
||||
end
|
||||
endfunction
|
||||
localparam [DEPTH-1:0] INIT_R = brev(INIT);
|
||||
|
||||
parameter _TECHMAP_CONSTMSK_L_ = 0;
|
||||
parameter _TECHMAP_CONSTVAL_L_ = 0;
|
||||
|
||||
wire CE;
|
||||
generate
|
||||
if (ENPOL == 0)
|
||||
assign CE = ~E;
|
||||
else if (ENPOL == 1)
|
||||
assign CE = E;
|
||||
else
|
||||
assign CE = 1'b1;
|
||||
if (DEPTH == 1) begin
|
||||
if (CLKPOL)
|
||||
FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
|
||||
else
|
||||
FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
|
||||
end else
|
||||
if (DEPTH <= 16) begin
|
||||
SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
|
||||
end else
|
||||
if (DEPTH > 17 && DEPTH <= 32) begin
|
||||
SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
|
||||
end else
|
||||
if (DEPTH > 33 && DEPTH <= 64) begin
|
||||
wire T0, T1, T2;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T2;
|
||||
else
|
||||
MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
|
||||
end else
|
||||
if (DEPTH > 65 && DEPTH <= 96) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T4;
|
||||
else begin
|
||||
MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
|
||||
MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
|
||||
MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
|
||||
end
|
||||
end else
|
||||
if (DEPTH > 97 && DEPTH < 128) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T6;
|
||||
else begin
|
||||
MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
|
||||
MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
|
||||
MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
|
||||
end
|
||||
end
|
||||
else if (DEPTH == 128) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
|
||||
SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T6;
|
||||
else begin
|
||||
wire T7, T8;
|
||||
MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
|
||||
MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
|
||||
MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
|
||||
end
|
||||
end
|
||||
else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin
|
||||
// Handle cases where fixed-length depth is
|
||||
// just 1 over a convenient value
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
|
||||
end
|
||||
else begin
|
||||
localparam lower_clog2 = $clog2((DEPTH+1)/2);
|
||||
localparam lower_depth = 2 ** lower_clog2;
|
||||
wire T0, T1, T2, T3;
|
||||
if (&_TECHMAP_CONSTMSK_L_) begin
|
||||
\$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(lower_depth-1), .E(E), .Q(T0));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(DEPTH-lower_depth-1), .E(E), .Q(Q), .SO(T3));
|
||||
end
|
||||
else begin
|
||||
\$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(L[lower_clog2-1:0]), .E(E), .Q(T0), .SO(T1));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L[lower_clog2-1:0]), .E(E), .Q(T2), .SO(T3));
|
||||
assign Q = L[lower_clog2] ? T2 : T0;
|
||||
end
|
||||
if (DEPTH == 2 * lower_depth)
|
||||
assign SO = T3;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module \$shiftx (A, B, Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
|
|
|
|||
|
|
@ -308,3 +308,42 @@ module RAM128X1D (
|
|||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk) if (WE) mem[A] <= D;
|
||||
endmodule
|
||||
|
||||
module SRL16E (
|
||||
output Q,
|
||||
input A0, A1, A2, A3, CE, CLK, D
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
||||
reg [15:0] r = INIT;
|
||||
assign Q = r[{A3,A2,A1,A0}];
|
||||
generate
|
||||
if (IS_CLK_INVERTED) begin
|
||||
always @(negedge CLK) if (CE) r <= { r[14:0], D };
|
||||
end
|
||||
else
|
||||
always @(posedge CLK) if (CE) r <= { r[14:0], D };
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module SRLC32E (
|
||||
output Q,
|
||||
output Q31,
|
||||
input [4:0] A,
|
||||
input CE, CLK, D
|
||||
);
|
||||
parameter [31:0] INIT = 32'h00000000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
||||
reg [31:0] r = INIT;
|
||||
assign Q31 = r[31];
|
||||
assign Q = r[A];
|
||||
generate
|
||||
if (IS_CLK_INVERTED) begin
|
||||
always @(negedge CLK) if (CE) r <= { r[30:0], D };
|
||||
end
|
||||
else
|
||||
always @(posedge CLK) if (CE) r <= { r[30:0], D };
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -135,8 +135,8 @@ function xtract_cell_decl()
|
|||
xtract_cell_decl ROM256X1
|
||||
xtract_cell_decl ROM32X1
|
||||
xtract_cell_decl ROM64X1
|
||||
xtract_cell_decl SRL16E
|
||||
xtract_cell_decl SRLC32E
|
||||
#xtract_cell_decl SRL16E
|
||||
#xtract_cell_decl SRLC32E
|
||||
xtract_cell_decl STARTUPE2 "(* keep *)"
|
||||
xtract_cell_decl USR_ACCESSE2
|
||||
xtract_cell_decl XADC
|
||||
|
|
|
|||
|
|
@ -3809,22 +3809,6 @@ module ROM64X1 (...);
|
|||
input A0, A1, A2, A3, A4, A5;
|
||||
endmodule
|
||||
|
||||
module SRL16E (...);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
output Q;
|
||||
input A0, A1, A2, A3, CE, CLK, D;
|
||||
endmodule
|
||||
|
||||
module SRLC32E (...);
|
||||
parameter [31:0] INIT = 32'h00000000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
output Q;
|
||||
output Q31;
|
||||
input [4:0] A;
|
||||
input CE, CLK, D;
|
||||
endmodule
|
||||
|
||||
(* keep *)
|
||||
module STARTUPE2 (...);
|
||||
parameter PROG_USR = "FALSE";
|
||||
|
|
|
|||
|
|
@ -22,21 +22,26 @@
|
|||
|
||||
`ifndef _NO_FFS
|
||||
|
||||
`ifndef _NO_POS_SR
|
||||
module \$_DFF_N_ (input D, C, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
|
||||
module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
|
||||
|
||||
module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
|
||||
module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
|
||||
|
||||
module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
|
||||
module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
|
||||
module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
|
||||
module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
|
||||
|
||||
module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
|
||||
module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
|
||||
module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
|
||||
module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
|
||||
`endif
|
||||
|
||||
module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
|
||||
module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
module \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
`endif
|
||||
|
||||
`endif
|
||||
|
||||
|
|
|
|||
|
|
@ -64,10 +64,13 @@ struct SynthXilinxPass : public Pass
|
|||
log(" (this feature is experimental and incomplete)\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" disable infering of block rams\n");
|
||||
log(" disable inference of block rams\n");
|
||||
log("\n");
|
||||
log(" -nodram\n");
|
||||
log(" disable infering of distributed rams\n");
|
||||
log(" disable inference of distributed rams\n");
|
||||
log("\n");
|
||||
log(" -nosrl\n");
|
||||
log(" disable inference of shift registers\n");
|
||||
log("\n");
|
||||
log(" -run <from_label>:<to_label>\n");
|
||||
log(" only run the commands between the labels (see below). an empty\n");
|
||||
|
|
@ -108,23 +111,28 @@ struct SynthXilinxPass : public Pass
|
|||
log(" techmap -map +/xilinx/drams_map.v\n");
|
||||
log("\n");
|
||||
log(" fine:\n");
|
||||
log(" opt -fast -full\n");
|
||||
log(" opt -fast\n");
|
||||
log(" memory_map\n");
|
||||
log(" dffsr2dff\n");
|
||||
log(" dff2dffe\n");
|
||||
log(" opt -full\n");
|
||||
log(" techmap -map +/xilinx/arith_map.v\n");
|
||||
log(" opt -fast\n");
|
||||
log("\n");
|
||||
log(" map_cells:\n");
|
||||
log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
|
||||
log(" pmux2shiftx (without '-nosrl' only)\n");
|
||||
log(" opt_expr -mux_undef (without '-nosrl' only)\n");
|
||||
log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
|
||||
log(" techmap -map +/xilinx/cells_map.v\n");
|
||||
log(" opt -fast\n");
|
||||
log(" clean\n");
|
||||
log("\n");
|
||||
log(" map_luts:\n");
|
||||
log(" techmap -map +/techmap.v\n");
|
||||
log(" opt -full\n");
|
||||
log(" techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
|
||||
log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
|
||||
log(" clean\n");
|
||||
log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v\n");
|
||||
log(" shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
|
||||
log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
|
||||
log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
|
||||
log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
|
||||
log("\n");
|
||||
|
|
@ -152,6 +160,7 @@ struct SynthXilinxPass : public Pass
|
|||
bool vpr = false;
|
||||
bool nobram = false;
|
||||
bool nodram = false;
|
||||
bool nosrl = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
|
|
@ -196,6 +205,10 @@ struct SynthXilinxPass : public Pass
|
|||
nodram = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nosrl") {
|
||||
nosrl = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc = "abc9";
|
||||
continue;
|
||||
|
|
@ -275,6 +288,21 @@ struct SynthXilinxPass : public Pass
|
|||
|
||||
if (check_label(active, run_from, run_to, "map_cells"))
|
||||
{
|
||||
if (!nosrl) {
|
||||
// shregmap operates on bit-level flops, not word-level,
|
||||
// so break those down here
|
||||
Pass::call(design, "simplemap t:$dff t:$dffe");
|
||||
// shregmap -tech xilinx can cope with $shiftx and $mux
|
||||
// cells for identifiying variable-length shift registers,
|
||||
// so attempt to convert $pmux-es to the former
|
||||
Pass::call(design, "pmux2shiftx");
|
||||
// pmux2shiftx can leave behind a $pmux with a single entry
|
||||
// -- need this to clean that up before shregmap
|
||||
Pass::call(design, "opt_expr -mux_undef");
|
||||
// shregmap with '-tech xilinx' infers variable length shift regs
|
||||
Pass::call(design, "shregmap -tech xilinx -minlen 3");
|
||||
}
|
||||
|
||||
Pass::call(design, "techmap -map +/xilinx/cells_map.v");
|
||||
Pass::call(design, "clean");
|
||||
}
|
||||
|
|
@ -282,14 +310,18 @@ struct SynthXilinxPass : public Pass
|
|||
if (check_label(active, run_from, run_to, "map_luts"))
|
||||
{
|
||||
Pass::call(design, "opt -full");
|
||||
Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
|
||||
Pass::call(design, "read_verilog +/xilinx/cells_box.v");
|
||||
Pass::call(design, "techmap -map +/techmap.v");
|
||||
if (abc == "abc9")
|
||||
Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
|
||||
else
|
||||
Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
|
||||
Pass::call(design, "clean");
|
||||
Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
|
||||
// This shregmap call infers fixed length shift registers after abc
|
||||
// has performed any necessary retiming
|
||||
if (!nosrl)
|
||||
Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
|
||||
Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
|
||||
Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
|
||||
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue