Miodrag Milanovic
8f221118d2
Add YS_ prefix to macros, add explanation and apply to older version as well
2020-03-13 17:19:54 +01:00
Eddie Hung
432a09af80
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
2020-03-13 08:17:39 -07:00
Miodrag Milanovic
7c54e61979
Use boost xpressive for gcc 4.8
2020-03-13 14:58:35 +01:00
Eddie Hung
b567f03c26
kernel: optimise Module::remove(const pool<RTLIL::Wire*>()
2020-03-12 16:00:34 -07:00
Eddie Hung
a076052fe4
kernel: SigPool to use const& + overloads to prevent implicit SigSpec
2020-03-12 16:00:34 -07:00
jiegec
7b679eecb3
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
David Shah
b8abf14376
Add ScriptPass::run_nocheck and use for abc9
...
Signed-off-by: David Shah <dave@ds0.me>
2020-03-09 14:34:22 +00:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
...
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Eddie Hung
0f4c1906bb
Small fixes
2020-02-27 10:29:53 -08:00
Eddie Hung
78929e8c3d
Fixes for older compilers
2020-02-27 10:17:29 -08:00
Eddie Hung
6bb3d9f9c0
Make TimingInfo::TimingInfo(SigBit) constructor explicit
2020-02-27 10:17:29 -08:00
Eddie Hung
9dcf204dec
TimingInfo: index by (port_name,offset)
2020-02-27 10:17:29 -08:00
Eddie Hung
7c3b4b80ea
Fix spacing
2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
Eddie Hung
a6fec9fe60
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
3ea5506f81
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
cda4acb544
abc9_ops: add and use new TimingInfo struct
2020-02-27 10:17:29 -08:00
Miodrag Milanović
036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass
...
Logger pass
2020-02-26 13:32:49 +01:00
Miodrag Milanovic
1c569fe06a
Remove duplicate warning detection
2020-02-23 10:56:27 +01:00
Alberto Gonzalez
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
Miodrag Milanovic
d079ab9d19
Handle expect no warnings together with expected
2020-02-22 10:52:46 +01:00
Miodrag Milanovic
70db8e9200
Prevent double error message
2020-02-17 16:46:34 +01:00
Miodrag Milanovic
5641b0248f
Option to expect no warnings
2020-02-17 15:36:06 +01:00
Miodrag Milanovic
be977cf7eb
No new error if already failing
2020-02-17 12:54:36 +01:00
Miodrag Milanovic
6b396e6455
remove whitespace
2020-02-14 13:12:05 +01:00
Miodrag Milanovic
31b7a9c312
Add expect option to logger command
2020-02-14 12:21:16 +01:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Claire Wolf
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental
...
Add log_experimental() and experimental() API and "yosys -x"
2020-01-29 15:25:03 +01:00
Eddie Hung
6d27d43727
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
Claire Wolf
5c2508cef8
Improve logging use of experimental features
...
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-28 17:51:50 +01:00
Claire Wolf
cef607c8b7
Add log_experimental() and experimental() API and "yosys -x"
...
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 18:27:47 +01:00
Claire Wolf
de6006fbc8
Merge pull request #1613 from porglezomp-misc/version-flag-alias
...
Add --version and -version as aliases for -V
2020-01-27 12:59:27 +01:00
Eddie Hung
ade57058f7
As before, only display MEM if Linux or FreeBSD
2020-01-14 11:38:48 -08:00
Eddie Hung
a901a5fb44
print_stats footer to return peak memory, option for including children
2020-01-14 11:25:23 -08:00
Eddie Hung
67c9c41f7e
Move abc9.* constpad entries to Abc9Pass::on_register()
2020-01-09 17:10:54 -08:00
Eddie Hung
dd718838bb
Merge remote-tracking branch 'origin/clifford/onpassreg' into eddie/abc9_scratchpad
2020-01-09 17:06:13 -08:00
Clifford Wolf
cd92a974f4
Add Pass::on_register() and Pass::on_shutdown()
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-09 21:36:34 +01:00
Eddie Hung
fbd9636e08
Add abc9.if.script.flow{,2} to constpad
2020-01-08 12:15:01 -08:00
Eddie Hung
a63e2508fc
Add RTLIL::constpad, init by yosys_setup(); use for abc9
2020-01-08 10:52:08 -08:00
Cassie Jones
b76b023584
Add --version and -version as aliases for -V
...
The flag --version is commonly accepted by command line tools.
The code for the version flags added here matches the pattern used for
the help flag aliases, for consistency.
Fixes #1612
2020-01-05 03:19:02 -05:00
Clifford Wolf
3edb2e708b
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-02 18:58:45 +01:00
whitequark
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
...
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
Eddie Hung
6bf7114bbd
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
2019-10-04 16:45:36 -07:00
Eddie Hung
279fd22ddf
Add Const::{begin,end,empty}()
2019-10-04 15:00:57 -07:00
Eddie Hung
62c66406ad
log_dump() to support State enum
2019-10-02 17:49:07 -07:00
Eddie Hung
d963e8c2c6
Fix typo
2019-09-30 15:18:40 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
...
Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Eddie Hung
d5f0794a53
Merge pull request #1414 from hzeller/improve-replace-with-empty-map
...
Avoid work in replace() if rules empty.
2019-09-29 19:35:23 -07:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Henner Zeller
8c2b4f0a50
Avoid work in replace() if rules empty.
...
This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382 .
Signed-off-by: Henner Zeller <h.zeller@acm.org>
2019-09-29 00:17:40 -07:00
