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Author SHA1 Message Date
Eddie Hung
0c003a3d0d Bump gcc from 4.8 to 4.9 as undefined reference 
... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
 2019-08-14 11:26:32 -07:00
Eddie Hung
5ec5f6dec7 Only sort leaves on non-ANDNOT/ORNOT cells 2019-08-14 11:25:56 -07:00
Eddie Hung
e2797f1308
Merge pull request #1294 from YosysHQ/revert-1288-eddie/fix_1284 
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"
 2019-08-14 10:42:18 -07:00
Eddie Hung
0e128510c0
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves" 2019-08-14 10:40:53 -07:00
Eddie Hung
aad97168b0 Fixes for reverting SigSpec helper functions 2019-08-14 10:22:33 -07:00
Eddie Hung
2f04beeeb5 Perform C -> PCIN optimisation after pattern matcher 2019-08-13 17:11:35 -07:00
Eddie Hung
1b0e68db94 Revert changes to RTLIL::SigSpec methods 2019-08-13 17:09:28 -07:00
Eddie Hung
e35dfc5ab5 Only swap ports if $mul and not $__mul 2019-08-13 16:52:15 -07:00
Marcin Kościelnicki
2d5d82e2b6 README updates 2019-08-13 21:47:27 +02:00
Marcin Kościelnicki
3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung
ed4b2834ef Add assign PCOUT = P to DSP48E1 2019-08-13 12:19:26 -07:00
Marcin Kościelnicki
49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Eddie Hung
0597a3ea23 Rename to XilinxDspPass 2019-08-13 10:23:07 -07:00
Eddie Hung
2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
Eddie Hung
19d6b8846f
Merge pull request #1288 from YosysHQ/eddie/fix_1284 
Since $_ANDNOT_ is not symmetric, do not sort leaves
 2019-08-13 09:06:11 -07:00
Clifford Wolf
0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
David Shah
edff79a25a xilinx: Rework labels for faster Verilator testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-13 10:29:42 +01:00
Marcin Kościelnicki
c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung
8a2480526f Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung
f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Miodrag Milanovic
5f561bdcb1 Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
Eddie Hung
e4a0971581 Since $_ANDNOT_ is not symmetric, do not sort leaves 2019-08-12 11:17:15 -07:00
Serge Bazanski
78b30bbb11
Merge pull request #1152 from 1138-4EB/feat-docker 
Dockerfile
 2019-08-12 15:09:25 +02:00
Eddie Hung
ba1a428f55
Merge pull request #1277 from YosysHQ/eddie/fix_1262 
opt_expr -fine to now trim LSBs of $alu cells too
 2019-08-11 22:10:17 -07:00
Eddie Hung
88d5185596 Merge remote-tracking branch 'origin/master' into eddie/fix_1262 2019-08-11 21:13:40 -07:00
Miodrag Milanovic
2897fe4d09 Fix formating 2019-08-11 17:05:24 +02:00
Miodrag Milanovic
ead2b52b5a one bit enable signal 2019-08-11 13:59:39 +02:00
Clifford Wolf
b25cf36856 Add YOSYS_NO_IDS_REFCNT configuration macro 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 12:23:16 +02:00
Miodrag Milanovic
aa0c37722a fix mixing signals on FF mapping 2019-08-11 11:40:15 +02:00
Clifford Wolf
390bf459fb Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Clifford Wolf
8222c5735e More improvements and cleanups in IdString subsystem 
- better use of "inline" keyword
- deprecate "sticky" IDs feature
- improve handling of empty ID
- add move constructor

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Clifford Wolf
6995914f3f Use ID() macro in all of passes/opt/ 
This was obtained by running the following SED command in passes/opt/
and then using "meld foo.cc foo.cc.orig" to manually fix all resulting
compiler errors.

sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Clifford Wolf
b5534b66c8 Improve API of ID() macro 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Miodrag Milanovic
853c755a0c Replaced custom step with setundef 2019-08-11 11:01:46 +02:00
Miodrag Milanovic
e609537e38 Fixed data width 2019-08-11 10:46:48 +02:00
Miodrag Milanovic
8c8100e0df Adding new pass to fix carry chain 2019-08-11 10:17:49 +02:00
Miodrag Milanovic
b3a91d6508 cleanup 2019-08-11 08:37:56 +02:00
Eddie Hung
c851dc1310
Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder 
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
 2019-08-10 14:18:16 -07:00
Eddie Hung
282cc77604 Wrong way around 2019-08-10 11:55:00 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung
02b0d328ad cover_list -> cover as per @cliffordwolf 2019-08-10 08:26:41 -07:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf
4f81213165
Merge pull request #1261 from YosysHQ/clifford/verific_init 
Automatically prune init attributes in verific front-end
 2019-08-10 09:47:25 +02:00
Clifford Wolf
05c46a31dc
Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell 
FIRRTL error on unsupported cell
 2019-08-10 09:47:10 +02:00
Clifford Wolf
a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc 
Add a few comments to document $alu and $lcu
 2019-08-10 09:46:46 +02:00
Clifford Wolf
465a59319a
Merge pull request #1272 from mmicko/travis_fix 
Propagate parameters for Travis build
 2019-08-10 09:45:26 +02:00
Clifford Wolf
b1e817e616
Merge pull request #1274 from YosysHQ/eddie/fix_1271 
Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
 2019-08-10 09:45:06 +02:00
Clifford Wolf
dad9514d86
Merge pull request #1276 from YosysHQ/clifford/fix1273 
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib
 2019-08-10 09:38:22 +02:00