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Author	SHA1	Message	Date
Ethan Mahintorabi	d10190606c	verilog: Lower required bison version to 3.6 ... We're currently on version 3.6 of bison at Google, and Yosys still correctly builds with it. This should better reflect the actual requirements rather than an overly restrictive check. If features from 3.8 are required it seems like bumping would be appropriate. Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2025-08-21 08:26:33 +01:00
Ethan Mahintorabi	7f0130efce	verilog: Fix missing sstream include ... Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2025-08-21 08:26:20 +01:00
github-actions[bot]	4926e846f6	Bump version	2025-08-21 00:22:37 +00:00
Emil J	025d7a5641	Merge pull request #5290 from rocallahan/opt-mux-perf ... Make `OptMuxtreePass` int-indexed vectors into hashtables	2025-08-20 20:00:26 +02:00
Jannis Harder	c9ad7b7ad0	Merge pull request #5284 from jix/fix_5282 ... check: Limit detailed cell edge checking for $pmux and $bmux	2025-08-20 14:27:19 +02:00
Emil J	ba8af7ad8f	Merge pull request #5302 from rocallahan/commutative-hash ... Improve commutative hashing.	2025-08-20 10:43:00 +02:00
Emil J. Tywoniak	01de9fb453	hashlib: extend unit test with subset collisions, shorten runtime	2025-08-20 00:08:23 +02:00
Robert O'Callahan	3a5742ffd2	Improve commutative hashing. ... The simple XOR `commutative_eat()` implementation produces a lot of collisions. https://www.preprints.org/manuscript/201710.0192/v1/download is a useful reference on this topic. Running the included `hashTest.cc` without the hashlib changes, I get 49,580,349 collisions. The 49,995,000 (i,j) pairs (0 <= i < 10000, i < j < 10000) hash into only 414,651 unique hash values. We get simple collisions like (0,1) colliding with (2,3). With the hashlib changes, we get only 707,099 collisions and 49,287,901 unique hash values. Much better! The `commutative_hash` implementation corresponds to `Sum(4)` in the paper mentioned above.	2025-08-19 21:45:52 +00:00
Emil J	b0d709f6cf	Merge pull request #5294 from rocallahan/precision-tests ... Add tests for dynamic precision and with with an int parameter	2025-08-19 16:42:49 +02:00
Miodrag Milanović	5fd9f54482	Merge pull request #5300 from donn/wheel_fixes ... wheels: bison 3.8 on almalinux + memory pressure easing	2025-08-19 11:44:12 +02:00
github-actions[bot]	bfc9a322e2	Bump version	2025-08-19 00:24:35 +00:00
Mohamed Gaber	2ed7a7aac9	wheels: fix PATH variables	2025-08-19 01:28:46 +03:00
Jannis Harder	6b94376daf	Merge pull request #5299 from YosysHQ/revert-5280-krys/ci_changes ... Revert "Workflow adjustments"	2025-08-18 21:50:19 +02:00
Mohamed Gaber	6cbd44daa5	wheels: bison 3.8 on almalinux + memory pressure easing ... - cibw now builds and uses bison 3.8.2 explicitly on platforms with no or out-of-date bison — AlmaLinux 8 only goes up to Bison 3.0 - cibw environment now includes `OPTFLAGS=-O3` to avoid generating debug info for abc, saving space in memory during linking - setup.py attempts to build `yosys-abc` independently first to avoid memory pressure from gigantic abc link step running in parallel with something else	2025-08-18 22:34:15 +03:00
Jannis Harder	b640a16b07	Revert "Workflow adjustments"	2025-08-18 20:39:00 +02:00
Jannis Harder	7c409e2d5a	Merge pull request #5285 from jix/abstract_initstates ... abstract: Add -initstates option	2025-08-18 15:39:09 +02:00
Robert O'Callahan	e0e70d1158	Remove some c_str() calls where they're no longer needed as parameters to stringf().	2025-08-18 14:20:31 +01:00
Emil J	f0ccc65820	Merge pull request #5297 from rocallahan/redundant-assignmap ... Remove redundant construction of `assign_map`.	2025-08-18 10:43:44 +02:00
Miodrag Milanović	1a52a714b4	Merge pull request #5280 from YosysHQ/krys/ci_changes ... Workflow adjustments	2025-08-18 10:17:12 +02:00
github-actions[bot]	d73cd78001	Bump version	2025-08-18 00:27:23 +00:00
Robert O'Callahan	3f2c4f6f83	Remove redundant construction of assign_map. ... We call 'assign_map.set()' below which wipes the `SigMap` and reconstructs it. This operation is expensive because it scans the whole module. I think it's better to make heavyweight operations more visible so I'm removing the less obvious operation.	2025-08-17 23:34:11 +00:00
KrystalDelusion	6d55ca204b	Merge pull request #5281 from suisseWalter/add_parameterised_cells_stat ... STAT: Add parameterised cells	2025-08-18 09:21:45 +12:00
clemens	9278bed853	removed copyright notice on lib file. ... Should be covered by the yosys license not anything else.	2025-08-16 09:40:03 +02:00
clemens	4e45b5e1bb	permit trailing comma	2025-08-16 09:40:03 +02:00
clemens	73d1177665	testcases ... one testcase for single parameter cells. one testcase for double parameter cells.	2025-08-16 09:40:03 +02:00
clemens	8b1f77ebd2	cleanup. printf to errors or warnings	2025-08-16 09:40:03 +02:00
clemens	50fe9dd7f2	clean parsing code	2025-08-16 09:40:03 +02:00
clemens	5fc0e77c3d	add functionality to be able to use parameterised cells. ... cells can have their area as a function of the input port width.	2025-08-16 09:40:03 +02:00
clemens	d8fb4da437	updated testcase	2025-08-16 09:32:08 +02:00
clemens	a6e0ab5ea5	Update (sequential) area to be only local without -hierarchy	2025-08-16 09:09:57 +02:00
suisseWalter	f5b219f59e	Update passes/cmds/stat.cc ... Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>	2025-08-16 08:36:06 +02:00
github-actions[bot]	d10fdc0ec5	Bump version	2025-08-16 00:24:02 +00:00
KrystalDelusion	7799c6e6ac	Merge pull request #5291 from YosysHQ/krys/rename_escape ... rename.cc: Fixup ports after -unescape	2025-08-16 12:19:49 +12:00
Robert O'Callahan	e906ea3f1b	Add tests for dynamic precision and with with an int parameter	2025-08-15 23:58:58 +00:00
KrystalDelusion	4a324e1da8	Merge pull request #5292 from rocallahan/wasm-varargs ... Fix vararg alignment	2025-08-16 10:29:36 +12:00
Emil J	70600bb596	Merge pull request #5239 from rocallahan/abc-incremental ... In the ABC pass, avoid scanning the entire module for each ABC run	2025-08-15 20:17:32 +02:00
Robert O'Callahan	6d62a1fff7	Fix vararg alignment	2025-08-15 05:43:53 +00:00
github-actions[bot]	bf625951d7	Bump version	2025-08-15 00:26:03 +00:00
Robert O'Callahan	dd88423334	Make OptMuxtree int-indexed vectors into hashtables ... For one of our large circuits, this reduced the time for an OPT_MUXTREE pass from 169s to 5s.	2025-08-14 23:09:15 +00:00
Krystine Sherwin	ec18d1aede	rename.cc: Fixup ports after -unescape	2025-08-15 10:48:32 +12:00
Robert O'Callahan	62c441107d	Build FfInitVals for the entire module once and use it for every ABC run.	2025-08-14 22:29:51 +00:00
Robert O'Callahan	2654bd5355	Compute is_port in AbcPass without iterating through all cells and wires in the module every time we run ABC. ... This does not scale when we run ABC thousands of times in a single AbcPass.	2025-08-14 22:29:45 +00:00
Robert O'Callahan	ac8259b02e	Preserve assign_map across ABC invocations. ... Currently `assign_map` is rebuilt from the module from scratch every time we invoke ABC. That doesn't scale when we do thousands of ABC runs over large modules. Instead, create it once and then maintain incrementally it as we update the module.	2025-08-14 22:27:04 +00:00
Robert O'Callahan	4de3ee093e	Mark kept FF output wires as ports directly instead of via the 'keep' attribute	2025-08-14 22:26:38 +00:00
Emil J	195d3ef940	Merge pull request #5100 from jix/rename_move_to_cell ... rename: add -move-to-cell option in -wire mode	2025-08-14 16:45:33 +02:00
Miodrag Milanovic	1dbf2df983	Add libfl-dev for CodeQL CI job	2025-08-14 09:15:43 +02:00
github-actions[bot]	a265b23ac0	Bump version	2025-08-14 00:25:16 +00:00
clemens	71307b4a51	add Testcases ... Fix existing testcases Fix edgecase where modules where counted as cells.	2025-08-13 14:46:01 +02:00
Emil J	dbb977aa8b	Merge pull request #5288 from YosysHQ/emil/demote-verilog-parser-errors-again ... verilog: demote some parser errors to warnings again	2025-08-13 12:52:50 +02:00
Emil J. Tywoniak	856fc43a87	rename: format vector slices consistently with HDL upto/downto direction	2025-08-13 11:11:53 +02:00