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Code Activity
14859 commits 122 branches 59 tags 43 MiB
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508 commits

Author SHA1 Message Date
Akash Levy
83234d24f7 Switch from Synopsys register naming to preserve 2024-11-11 17:06:56 -08:00
Akash Levy
894c9816d3 Improve naming: big fix 2024-11-11 17:06:11 -08:00
Alain Dargelas
615f523ef4 pass no_split_complex_ports to hierarchy command 2024-10-29 13:37:03 -07:00
Akash Levy
5e606722e3 Get autoidx reset working 2024-10-28 16:30:47 -07:00
Akash Levy
038c562493 VHDL support fix 2024-10-25 11:32:52 -07:00
Akash Levy
8e667e2e9f Add documentation for VHDL library directory 2024-10-23 23:53:21 -07:00
Akash Levy
17c8567b02 Really tiny fixes 2024-10-23 22:03:00 -07:00
Akash Levy
3d127dff4a Add set VHDL default library path 2024-10-21 01:22:56 -07:00
Akash Levy
c94eac14b9 Remove GHDL and add mixed SV-VHDL support 2024-10-20 23:29:33 -07:00
Akash Levy
e2659247fc Verific UPF eval working 2024-10-17 04:40:38 -07:00
Akash Levy
469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J
caf56ca3e8
Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip 
Represent string constants as strings
 2024-10-14 06:42:54 -07:00
Emil J. Tywoniak
785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Miodrag Milanovic
8d2b63bb8a Set VHDL assert condition initial state if fed by FF 2024-10-11 16:32:21 +02:00
Akash Levy
48cb802599 Undo bound removal 2024-10-10 13:34:18 -07:00
Akash Levy
dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Akash Levy
5038bfa2af Fix minor whitespace thing 2024-10-03 00:29:16 -07:00
Akash Levy
ec296736f5 Simplify multiport 2024-10-02 22:19:09 -07:00
Akash Levy
400ae0bbab Prune RAM dimensions 2024-10-02 03:44:57 -07:00
Akash Levy
8bf86e8d1f Undo 2024-10-02 03:30:30 -07:00
Akash Levy
ff0fd570d8 Revert mem but fix Verific frontend to remove ugliness 2024-10-02 01:17:01 -07:00
Akash Levy
0610d6ccc2 Smallfix to get GHDL working 2024-09-27 06:38:42 -07:00
Akash Levy
bb2cdd61fe Fix GHDL and bump yosys-slang 2024-09-27 04:43:59 -07:00
Akash Levy
5a27db1463 Smallfix 2024-09-27 03:31:30 -07:00
Akash Levy
f6d577aed1 Fix GHDL support 2024-09-27 03:14:15 -07:00
Akash Levy
0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy
0b8d951493 Add synopsys VHDL libs by default in GHDL 2024-09-23 04:05:27 -07:00
Akash Levy
69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy
d655766c49 Smallfix 2024-09-22 06:57:28 -07:00
Akash Levy
89f9035a98 Fix VHDL checking 2024-09-22 06:45:47 -07:00
Akash Levy
7d5dac7255 More apt location for whereami 2024-09-22 06:02:20 -07:00
Akash Levy
f1ab51ce5b Clean up and remove hdl_file_sort 2024-09-22 05:58:17 -07:00
Akash Levy
f0b1d2cac5 Small changes 2024-09-22 01:11:26 -07:00
Akash Levy
4cf9bb86ca Smallfix 2024-09-19 01:04:29 -07:00
Akash Levy
7988a61f8c Use enable debug and switch order of Verific opt passes 2024-09-19 00:48:31 -07:00
Akash Levy
2d139c8735 Smallfix to remove top/bottom-bound attributes 2024-09-18 14:46:13 -07:00
Akash Levy
44789c9f6c Move ram opt around 2024-09-16 18:56:48 -07:00
Akash Levy
285c8a3f66
Merge branch 'YosysHQ:main' into main 2024-09-12 11:14:15 -07:00
Roland Coeurjoly
bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Akash Levy
ce95ec1f9e Add VHDL support via GHDL call 2024-09-05 13:24:38 -07:00
Akash Levy
6e46a56720 Fix Verific warning 2024-08-21 16:55:44 -07:00
Akash Levy
dba9a26cf3 Make default macros optional 2024-08-21 00:50:10 -07:00
Akash Levy
68b3ad4bd3 Display resource sharing count 2024-08-06 02:27:09 -07:00
Akash Levy
c0af4604bc Update Yosys 2024-07-30 16:55:18 -07:00
Miodrag Milanović
3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Miodrag Milanovic
405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
Akash Levy
f790b75c19 Don't preserve user nets and update Verific tree balancing 2024-07-25 06:01:06 -07:00
Miodrag Milanovic
9566709426 Initialize extensions when verific pass is registered 2024-07-25 11:25:17 +02:00
Akash Levy
f1114cc98c Simplify ignores 2024-07-24 02:14:11 -07:00
Miodrag Milanovic
c94aa719d9 VHDL is case insensitive, make sure netlist name is proper 2024-07-18 16:56:52 +02:00