3953 commits

Author	SHA1	Message	Date
Clifford Wolf	3aa003c8e9	Using "NOT" instead of "INV" as cell name in default abc genlib file	2014-09-19 13:15:31 +02:00
Clifford Wolf	f7bb8f244b	Alphabetically sort port names in "show" output	2014-09-19 11:13:10 +02:00
Clifford Wolf	f56b92818b	Do not run "scorr" in "abc -fast"	2014-09-18 19:00:21 +02:00
Clifford Wolf	815fab9d71	Added "abc -fast"	2014-09-18 12:57:37 +02:00
Clifford Wolf	9ae559b990	Fixed $_NOR vs. $_NOR_ typo in abc.cc	2014-09-16 12:45:05 +02:00
Clifford Wolf	ae02d9cb9a	Fixed $memwr/$memrd order in memory_dff	2014-09-16 12:40:58 +02:00
Clifford Wolf	b86410b2ab	More aggressive $macc merging in alumacc	2014-09-15 12:42:11 +02:00
Clifford Wolf	b470c480e9	Added the obvious optimizations to alumacc $macc generator	2014-09-15 12:22:03 +02:00
Clifford Wolf	fcbda07411	Improved maccmap tree bit packing	2014-09-15 12:00:19 +02:00
Clifford Wolf	2cbdbaad1f	Fixed wreduce $shiftx handling	2014-09-15 11:29:09 +02:00
Clifford Wolf	7e156a5419	Fixed techmap_wrap for techmap_celltype	2014-09-14 15:34:36 +02:00
Clifford Wolf	014bb34e0e	Various fixes/cleanups in alumacc and maccmap	2014-09-14 14:49:53 +02:00
Clifford Wolf	124e759280	Added techmap_wrap attribute	2014-09-14 14:49:26 +02:00
Clifford Wolf	b34ca15185	alumacc fix for $pos cells	2014-09-14 14:00:14 +02:00
Clifford Wolf	0df1d9ad72	Extract $alu cells in alumacc	2014-09-14 13:23:44 +02:00
Clifford Wolf	7b16c63101	Merge $macc cells in alumacc pass	2014-09-14 11:21:37 +02:00
Clifford Wolf	0b72f0acb1	Basic $macc extract in alumacc	2014-09-14 10:45:28 +02:00
Clifford Wolf	ff157fb74f	alumacc skeleton	2014-09-14 10:02:00 +02:00
Clifford Wolf	aab0e3bf70	Cleanup in wreduce	2014-09-14 10:01:30 +02:00
Clifford Wolf	af0c8873bb	Added $lcu cell type	2014-09-08 13:31:04 +02:00
Clifford Wolf	d46bac3305	Added "$fa" cell type	2014-09-08 12:15:39 +02:00
Clifford Wolf	1a88e47396	Trim msb/lsb zero bits from full adder in maccmap	2014-09-08 11:21:58 +02:00
Clifford Wolf	6747a7047e	Added "test_cell -const"	2014-09-08 11:12:39 +02:00
Clifford Wolf	c50b841b29	Added 'techmap_maccmap' techmap attribute	2014-09-07 18:23:37 +02:00
Clifford Wolf	015dcdc84c	Added "maccmap" command	2014-09-07 18:23:04 +02:00
Clifford Wolf	15b3c54fea	Added "test_cell -nosat"	2014-09-07 17:05:41 +02:00
Clifford Wolf	9329a76818	Various bug fixes (related to $macc model testing)	2014-09-06 20:30:46 +02:00
Clifford Wolf	fa64942018	Added $macc SAT model	2014-09-06 19:44:11 +02:00
Clifford Wolf	b847ec8a0b	Added $macc cell type	2014-09-06 15:47:46 +02:00
Clifford Wolf	34af6a1303	Merge branch 'master' of github.com:cliffordwolf/yosys	2014-09-06 11:46:44 +02:00
Clifford Wolf	e1743b3bac	Added "test_cell -script"	2014-09-06 11:46:07 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	f5a40e7043	Fixed "opt_const -fine" for $pos cells	2014-09-04 08:55:58 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	5733f4a39d	Fixed "test_cells -vlog"	2014-09-03 13:43:37 +02:00
Clifford Wolf	f1869667ca	Improvements in "test_cell -vlog"	2014-09-02 23:21:15 +02:00
Clifford Wolf	66bf2bb92e	Added test_cell -vlog	2014-09-02 22:49:43 +02:00
Clifford Wolf	acd7a99aef	Added SAT testing to test_cell eval stage	2014-09-02 17:28:13 +02:00
Clifford Wolf	37fe7c7bdf	Removed references to yosys-svgviewer from docs	2014-09-02 04:03:06 +02:00
Clifford Wolf	9f00a0cd2d	Using "xdot" instead of "yosys-svgviewer" in show command	2014-09-02 03:28:46 +02:00
Clifford Wolf	630befdf6d	Added $alu support to test_cell	2014-09-01 16:36:04 +02:00
Clifford Wolf	c7f81e4e49	Added "test_cell -simlib -v"	2014-09-01 15:37:21 +02:00
Clifford Wolf	826fdb34d8	Added "techmap -autoproc"	2014-09-01 15:36:29 +02:00
Clifford Wolf	27a1bfbec6	Fixes in old SAT example.ys	2014-09-01 11:45:47 +02:00
Clifford Wolf	d5148f2e01	Moved "share" and "wreduce" to passes/opt/	2014-09-01 11:45:26 +02:00
Clifford Wolf	e07698818d	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data	2014-09-01 11:36:02 +02:00
Clifford Wolf	e3664066d5	Added eval testing to test_cell	2014-08-31 18:08:42 +02:00
Clifford Wolf	8649b57b6f	Added $lut support in test_cell, techmap, satgen	2014-08-31 17:43:31 +02:00
Clifford Wolf	2a1b08aeb3	Added design->scratchpad	2014-08-30 19:37:12 +02:00
Clifford Wolf	6ff46323a3	Improved write address decoder generation memory_map	2014-08-30 18:18:15 +02:00