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Corrected spelling mistakes found by lintian

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This commit is contained in:
Ruben Undheim 2014-09-06 08:47:06 +02:00
parent 01ef34c147
commit 79cbf9067c
22 changed files with 39 additions and 39 deletions
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2
passes/cmds/scc.cc
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@ -216,7 +216,7 @@ struct SccPass : public Pass {
log("\n");
log(" -all_cell_types\n");
log(" Usually this command only considers internal non-memory cells. With\n");
log(" this option set, all cells are considered. For unkown cells all ports\n");
log(" this option set, all cells are considered. For unknown cells all ports\n");
log(" are assumed to be bidirectional 'inout' ports.\n");
log("\n");
log(" -set_attr <name> <value>\n");

4
passes/cmds/select.cc
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@ -985,7 +985,7 @@ struct SelectPass : public Pass {
log(" (i.e. select all cells connected to selected wires and select all\n");
log(" wires connected to selected cells) The rules specify which cell\n");
log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n");
log(" and a '+' for inclusion, followed by an optional comma seperated\n");
log(" and a '+' for inclusion, followed by an optional comma separated\n");
log(" list of cell types followed by an optional comma separated list of\n");
log(" cell ports in square brackets. a rule can also be just a cell or wire\n");
log(" name that limits the expansion (is included but does not go beyond).\n");
@ -1089,7 +1089,7 @@ struct SelectPass : public Pass {
continue;
}
if (arg.size() > 0 && arg[0] == '-')
log_cmd_error("Unkown option %s.\n", arg.c_str());
log_cmd_error("Unknown option %s.\n", arg.c_str());
select_stmt(design, arg);
sel_str += " " + arg;
}

4
passes/cmds/splice.cc
View file

@ -251,12 +251,12 @@ struct SplicePass : public Pass {
log("\n");
log(" -sel_by_cell\n");
log(" only select the cell ports to rewire by the cell. if the selection\n");
log(" contains a cell, than all cell inputs are rewired, if neccessary.\n");
log(" contains a cell, than all cell inputs are rewired, if necessary.\n");
log("\n");
log(" -sel_by_wire\n");
log(" only select the cell ports to rewire by the wire. if the selection\n");
log(" contains a wire, than all cell ports driven by this wire are wired,\n");
log(" if neccessary.\n");
log(" if necessary.\n");
log("\n");
log(" -sel_any_bit\n");
log(" it is sufficient if the driver of any bit of a cell port is selected.\n");

2
passes/cmds/splitnets.cc
View file

@ -76,7 +76,7 @@ struct SplitnetsPass : public Pass {
log(" -format char1[char2[char3]]\n");
log(" the first char is inserted between the net name and the bit index, the\n");
log(" second char is appended to the netname. e.g. -format () creates net\n");
log(" names like 'mysignal(42)'. the 3rd character is the range seperation\n");
log(" names like 'mysignal(42)'. the 3rd character is the range separation\n");
log(" character when creating multi-bit wires. the default is '[]:'.\n");
log("\n");
log(" -ports\n");

2
passes/fsm/fsm_recode.cc
View file

@ -55,7 +55,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
if (encoding != "none" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") {
log(" unkown encoding `%s': using auto instead.\n", encoding.c_str());
log(" unknown encoding `%s': using auto instead.\n", encoding.c_str());
encoding = "auto";
}

8
passes/hierarchy/hierarchy.cc
View file

@ -216,7 +216,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
int idx = it.second.first, num = it.second.second;
if (design->modules_.count(cell->type) == 0)
log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
RTLIL::Module *mod = design->modules_[cell->type];
@ -232,7 +232,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
}
}
if (mod->wires_.count(portname) == 0)
log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
int port_size = mod->wires_.at(portname)->width;
if (conn_size == port_size)
continue;
@ -294,7 +294,7 @@ struct HierarchyPass : public Pass {
log(" hierarchy [-check] [-top <module>]\n");
log(" hierarchy -generate <cell-types> <port-decls>\n");
log("\n");
log("In parametric designs, a module might exists in serveral variations with\n");
log("In parametric designs, a module might exists in several variations with\n");
log("different parameter values. This pass looks at all modules in the current\n");
log("design an re-runs the language frontends for the parametric modules as\n");
log("needed.\n");
@ -309,7 +309,7 @@ struct HierarchyPass : public Pass {
log("\n");
log(" -libdir <directory>\n");
log(" search for files named <module_name>.v in the specified directory\n");
log(" for unkown modules and automatically run read_verilog for each\n");
log(" for unknown modules and automatically run read_verilog for each\n");
log(" unknown module.\n");
log("\n");
log(" -keep_positionals\n");

2
passes/memory/memory_share.cc
View file

@ -720,7 +720,7 @@ struct MemorySharePass : public Pass {
log(" address, then this feedback path is converted to a write port with\n");
log(" byte/part enable signals.\n");
log("\n");
log(" - When multiple write ports access the same adress then this is converted\n");
log(" - When multiple write ports access the same address then this is converted\n");
log(" to a single write port with a more complex data and/or enable logic path.\n");
log("\n");
log(" - When multiple write ports are never accessed at the same time (a SAT\n");

4
passes/opt/opt_clean.cc
View file

@ -367,10 +367,10 @@ struct CleanPass : public Pass {
log("\n");
log("This is identical to 'opt_clean', but less verbose.\n");
log("\n");
log("When commands are seperated using the ';;' token, this command will be executed\n");
log("When commands are separated using the ';;' token, this command will be executed\n");
log("between the commands.\n");
log("\n");
log("When commands are seperated using the ';;;' token, this command will be executed\n");
log("When commands are separated using the ';;;' token, this command will be executed\n");
log("in -purge mode between the commands.\n");
log("\n");
}

2
passes/sat/sat.cc
View file

@ -874,7 +874,7 @@ struct SatPass : public Pass {
log(" -set-def-at <N> <signal>\n");
log(" -set-any-undef-at <N> <signal>\n");
log(" -set-all-undef-at <N> <signal>\n");
log(" add undef contraints in the given timestep.\n");
log(" add undef constraints in the given timestep.\n");
log("\n");
log(" -set-init <signal> <value>\n");
log(" set the initial value for the register driving the signal to the value\n");