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Removed $bu0 cell type

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This commit is contained in:
Clifford Wolf 2014-09-04 02:07:52 +02:00
parent b9cb483f3e
commit 8927aa6148
18 changed files with 27 additions and 103 deletions
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2
passes/cmds/stat.cc
View file

@ -99,7 +99,7 @@ namespace
if (width_mode)
{
if (cell_type.in("$not", "$pos", "$bu0", "$neg",
if (cell_type.in("$not", "$pos", "$neg",
"$logic_not", "$logic_and", "$logic_or",
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
"$lut", "$and", "$or", "$xor", "$xnor",

10
passes/opt/opt_const.cc
View file

@ -181,7 +181,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
log("\n");
}
cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str());
cover_list("opt.opt_const.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str());
module->remove(cell);
did_something = true;
@ -236,7 +236,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (do_fine)
{
if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" ||
if (cell->type == "$not" || cell->type == "$pos" ||
cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")
if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map))
goto next_cell;
@ -586,7 +586,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (!keepdc)
{
bool identity_bu0 = false;
bool identity_wrt_a = false;
bool identity_wrt_b = false;
@ -607,7 +606,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
if (b.is_fully_const() && b.as_bool() == false)
identity_wrt_a = true, identity_bu0 = true;
identity_wrt_a = true;
}
if (cell->type == "$mul")
@ -646,7 +645,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
}
cell->type = identity_bu0 ? "$bu0" : "$pos";
cell->type = "$pos";
cell->unsetPort("\\B");
cell->parameters.erase("\\B_WIDTH");
cell->parameters.erase("\\B_SIGNED");
@ -840,7 +839,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
FOLD_2ARG_CELL(pow)
FOLD_1ARG_CELL(pos)
FOLD_1ARG_CELL(bu0)
FOLD_1ARG_CELL(neg)
// be very conservative with optimizing $mux cells as we do not want to break mux trees

1
passes/opt/share.cc
View file

@ -923,7 +923,6 @@ struct SharePass : public Pass {
config.generic_uni_ops.insert("$not");
// config.generic_uni_ops.insert("$pos");
// config.generic_uni_ops.insert("$bu0");
config.generic_uni_ops.insert("$neg");
config.generic_cbin_ops.insert("$and");

6
passes/opt/wreduce.cc
View file

@ -37,7 +37,7 @@ struct WreduceConfig
WreduceConfig()
{
supported_cell_types << "$not" << "$pos" << "$bu0" << "$neg";
supported_cell_types << "$not" << "$pos" << "$neg";
supported_cell_types << "$and" << "$or" << "$xor" << "$xnor";
supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx";
supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt";
@ -181,7 +181,7 @@ struct WreduceWorker
int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1;
int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1;
if (cell->type.in("$not", "$pos", "$bu0", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y")));
max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y")));
}
@ -216,7 +216,7 @@ struct WreduceWorker
}
}
if (cell->type.in("$pos", "$bu0", "$add", "$mul", "$and", "$or", "$xor"))
if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor"))
{
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();

13
passes/techmap/simplemap.cc
View file

@ -45,16 +45,6 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
}
static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
@ -386,7 +376,6 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
{
mappers["$not"] = simplemap_not;
mappers["$pos"] = simplemap_pos;
mappers["$bu0"] = simplemap_bu0;
mappers["$and"] = simplemap_bitop;
mappers["$or"] = simplemap_bitop;
mappers["$xor"] = simplemap_bitop;
@ -420,7 +409,7 @@ struct SimplemapPass : public Pass {
log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
log("primitives. The following internal cell types are mapped by this pass:\n");
log("\n");
log(" $not, $pos, $bu0, $and, $or, $xor, $xnor\n");
log(" $not, $pos, $and, $or, $xor, $xnor\n");
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
log(" $logic_not, $logic_and, $logic_or, $mux\n");
log(" $sr, $dff, $dffsr, $adff, $dlatch\n");

1
passes/tests/test_cell.cc
View file

@ -441,7 +441,6 @@ struct TestCellPass : public Pass {
cell_types["$not"] = "ASY";
cell_types["$pos"] = "ASY";
cell_types["$bu0"] = "ASY";
cell_types["$neg"] = "ASY";
cell_types["$and"] = "ABSY";