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https://github.com/YosysHQ/yosys
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Added "maccmap" command
This commit is contained in:
Clifford Wolf
parent
15b3c54fea
commit
015dcdc84c
2 changed files with 319 additions and 0 deletions
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@ -8,6 +8,7 @@ ifneq ($(SMALL),1)
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OBJS += passes/techmap/iopadmap.o
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OBJS += passes/techmap/hilomap.o
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OBJS += passes/techmap/extract.o
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OBJS += passes/techmap/maccmap.o
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endif
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GENFILES += passes/techmap/techmap.inc
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318
passes/techmap/maccmap.cc
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318
passes/techmap/maccmap.cc
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@ -0,0 +1,318 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/macc.h"
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extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
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struct MaccmapWorker
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{
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std::vector<std::set<RTLIL::SigBit>> bits;
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RTLIL::Module *module;
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int width;
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MaccmapWorker(RTLIL::Module *module, int width) : module(module), width(width)
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{
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bits.resize(width);
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}
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void add(RTLIL::SigBit bit, int position)
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{
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if (position >= width || bit == RTLIL::S0)
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return;
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if (bits.at(position).count(bit)) {
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bits.at(position).erase(bit);
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add(bit, position+1);
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} else {
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bits.at(position).insert(bit);
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}
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}
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void add(RTLIL::SigSpec a, bool is_signed, bool do_subtract)
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{
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a.extend(width, is_signed);
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if (do_subtract) {
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a = module->Not(NEW_ID, a);
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add(RTLIL::S1, 0);
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}
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for (int i = 0; i < width; i++)
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add(a[i], i);
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}
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void add(RTLIL::SigSpec a, RTLIL::SigSpec b, bool is_signed, bool do_subtract)
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{
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if (SIZE(a) < SIZE(b))
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std::swap(a, b);
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a.extend(width, is_signed);
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if (SIZE(b) > width)
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b.extend(width, is_signed);
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for (int i = 0; i < SIZE(b); i++)
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if (is_signed && i+1 == SIZE(b))
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{
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a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
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add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
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add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract);
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}
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else
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{
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add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
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a = {a.extract(0, width-1), RTLIL::S0};
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}
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}
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void fulladd(RTLIL::SigSpec &in1, RTLIL::SigSpec &in2, RTLIL::SigSpec &in3, RTLIL::SigSpec &out1, RTLIL::SigSpec &out2)
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{
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RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2);
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out1 = module->Xor(NEW_ID, t1, in3);
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RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2);
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RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1);
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out2 = module->Or(NEW_ID, t2, t3);
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}
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int tree_bit_slots(int n)
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{
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#if 0
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int retval = 0;
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while (n > 2) {
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retval += n / 3;
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n = 2*(n / 3) + (n % 3);
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}
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return retval;
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#else
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return std::max(n - 2, 0);
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#endif
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}
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RTLIL::SigSpec synth()
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{
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std::vector<RTLIL::SigSpec> summands;
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std::vector<RTLIL::SigBit> tree_sum_bits;
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int unique_tree_bits = 0;
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while (1)
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{
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RTLIL::SigSpec summand(0, width);
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bool got_data_bits = false;
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for (int i = 0; i < width; i++)
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if (!bits.at(i).empty()) {
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auto it = bits.at(i).begin();
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summand[i] = *it;
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bits.at(i).erase(it);
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got_data_bits = true;
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}
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if (!got_data_bits)
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break;
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summands.push_back(summand);
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int free_bit_slots = tree_bit_slots(SIZE(summands)) - SIZE(tree_sum_bits);
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for (int i = 0; i < width && (1 << i) <= free_bit_slots; i++)
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while (!bits.at(i).empty() && (1 << i) <= free_bit_slots) {
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auto it = bits.at(i).begin();
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RTLIL::SigBit bit = *it;
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bits.at(i).erase(it);
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for (int k = 0; k < (1 << i); k++, free_bit_slots--)
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tree_sum_bits.push_back(bit);
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unique_tree_bits++;
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}
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}
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if (!tree_sum_bits.empty())
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log(" packed %d (%d) bits into adder tree\n", SIZE(tree_sum_bits), unique_tree_bits);
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if (SIZE(summands) == 0)
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return RTLIL::SigSpec(0, width);
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if (SIZE(summands) == 1)
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return summands.front();
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while (SIZE(summands) > 2)
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{
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std::vector<RTLIL::SigSpec> new_summands;
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for (int i = 0; i < SIZE(summands); i += 3)
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if (i+2 < SIZE(summands)) {
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RTLIL::SigSpec in1 = summands[i];
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RTLIL::SigSpec in2 = summands[i+1];
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RTLIL::SigSpec in3 = summands[i+2];
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RTLIL::SigSpec out1, out2;
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fulladd(in1, in2, in3, out1, out2);
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RTLIL::SigBit extra_bit = RTLIL::S0;
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if (!tree_sum_bits.empty()) {
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extra_bit = tree_sum_bits.back();
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tree_sum_bits.pop_back();
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}
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new_summands.push_back(out1);
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new_summands.push_back({out2.extract(0, width-1), extra_bit});
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} else {
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new_summands.push_back(summands[i]);
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i -= 2;
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}
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summands.swap(new_summands);
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}
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return module->Add(NEW_ID, summands.front(), summands.back());
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}
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};
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void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
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{
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int width = SIZE(cell->getPort("\\Y"));
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Macc macc;
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macc.from_cell(cell);
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RTLIL::SigSpec all_input_bits;
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all_input_bits.append(cell->getPort("\\A"));
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all_input_bits.append(cell->getPort("\\B"));
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if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) {
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module->connect(cell->getPort("\\Y"), RTLIL::SigSpec(RTLIL::Sx, width));
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return;
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}
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for (auto &port : macc.ports)
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if (SIZE(port.in_b) == 0)
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log(" %s %s (%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a),
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SIZE(port.in_a), port.is_signed ? "signed" : "unsigned");
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else
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log(" %s %s * %s (%dx%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), log_signal(port.in_b),
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SIZE(port.in_a), SIZE(port.in_b), port.is_signed ? "signed" : "unsigned");
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if (SIZE(macc.bit_ports) != 0)
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log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), SIZE(macc.bit_ports));
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if (unmap)
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{
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typedef std::pair<RTLIL::SigSpec, bool> summand_t;
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std::vector<summand_t> summands;
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for (auto &port : macc.ports) {
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summand_t this_summand;
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if (SIZE(port.in_b)) {
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this_summand.first = module->addWire(NEW_ID, width);
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module->addMul(NEW_ID, port.in_a, port.in_b, this_summand.first, port.is_signed);
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} else if (SIZE(port.in_a) != width) {
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this_summand.first = module->addWire(NEW_ID, width);
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module->addPos(NEW_ID, port.in_a, this_summand.first, port.is_signed);
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} else {
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this_summand.first = port.in_a;
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}
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this_summand.second = port.do_subtract;
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summands.push_back(this_summand);
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}
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for (auto &bit : macc.bit_ports)
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summands.push_back(summand_t(bit, false));
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if (SIZE(summands) == 0)
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summands.push_back(summand_t(RTLIL::SigSpec(0, width), false));
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while (SIZE(summands) > 1)
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{
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std::vector<summand_t> new_summands;
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for (int i = 0; i < SIZE(summands); i += 2) {
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if (i+1 < SIZE(summands)) {
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summand_t this_summand;
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this_summand.first = module->addWire(NEW_ID, width);
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this_summand.second = summands[i].second && summands[i+1].second;
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if (summands[i].second == summands[i+1].second)
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module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
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else if (summands[i].second)
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module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first);
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else if (summands[i+1].second)
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module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
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else
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log_abort();
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new_summands.push_back(this_summand);
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} else
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new_summands.push_back(summands[i]);
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}
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summands.swap(new_summands);
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}
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if (summands.front().second)
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module->addNeg(NEW_ID, summands.front().first, cell->getPort("\\Y"));
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else
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module->connect(cell->getPort("\\Y"), summands.front().first);
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}
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else
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{
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MaccmapWorker worker(module, width);
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for (auto &port : macc.ports)
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if (SIZE(port.in_b) == 0)
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worker.add(port.in_a, port.is_signed, port.do_subtract);
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else
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worker.add(port.in_a, port.in_b, port.is_signed, port.do_subtract);
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for (auto &bit : macc.bit_ports)
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worker.add(bit, 0);
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module->connect(cell->getPort("\\Y"), worker.synth());
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}
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}
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struct MaccmapPass : public Pass {
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MaccmapPass() : Pass("maccmap", "mapping macc cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" maccmap [-unmap] [selection]\n");
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log("\n");
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log("This pass maps $macc cells to yosys gate primitives. When the -unmap option is\n");
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log("used then the $macc cell is mapped to $and, $sub, etc. cells instead.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool unmap_mode = false;
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log_header("Executing MACCMAP pass (map $macc cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-unmap") {
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unmap_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules())
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for (auto cell : mod->selected_cells())
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if (cell->type == "$macc") {
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log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
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maccmap(mod, cell, unmap_mode);
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mod->remove(cell);
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}
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}
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} MaccmapPass;
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