mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 17:15:33 +00:00
Code Activity

Added "$fa" cell type

Browse source
This commit is contained in:
Clifford Wolf 2014-09-08 12:15:39 +02:00
parent 1a88e47396
commit d46bac3305
8 changed files with 164 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

20
passes/techmap/maccmap.cc
View file

@ -106,12 +106,20 @@ struct MaccmapWorker
in2 = in2.extract(start_index, stop_index-start_index);
in3 = in3.extract(start_index, stop_index-start_index);
RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2);
out1 = {out_zeros_msb, module->Xor(NEW_ID, t1, in3), out_zeros_lsb};
int width = SIZE(in1);
RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2);
RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1);
out2 = {out_zeros_msb, module->Or(NEW_ID, t2, t3), out_zeros_lsb};
RTLIL::Cell *cell = module->addCell(NEW_ID, "$fa");
cell->setParam("\\WIDTH", width);
cell->setPort("\\A", in1);
cell->setPort("\\B", in2);
cell->setPort("\\C", in3);
cell->setPort("\\Y", w1);
cell->setPort("\\X", w2);
out1 = {out_zeros_msb, w1, out_zeros_lsb};
out2 = {out_zeros_msb, w2, out_zeros_lsb};
}
}
@ -198,6 +206,8 @@ struct MaccmapWorker
summands.swap(new_summands);
}
log_assert(tree_sum_bits.empty());
return module->Add(NEW_ID, summands.front(), summands.back());
}
};

31
passes/tests/test_cell.cc
View file

@ -39,6 +39,36 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
RTLIL::Wire *wire;
if (cell_type == "$fa")
{
int width = 1 + xorshift32(8);
wire = module->addWire("\\A");
wire->width = width;
wire->port_input = true;
cell->setPort("\\A", wire);
wire = module->addWire("\\B");
wire->width = width;
wire->port_input = true;
cell->setPort("\\B", wire);
wire = module->addWire("\\C");
wire->width = width;
wire->port_input = true;
cell->setPort("\\C", wire);
wire = module->addWire("\\X");
wire->width = width;
wire->port_output = true;
cell->setPort("\\X", wire);
wire = module->addWire("\\Y");
wire->width = width;
wire->port_output = true;
cell->setPort("\\Y", wire);
}
if (cell_type == "$macc")
{
Macc macc;
@ -603,6 +633,7 @@ struct TestCellPass : public Pass {
cell_types["$lut"] = "*";
cell_types["$alu"] = "ABSY";
cell_types["$macc"] = "*";
cell_types["$fa"] = "*";
for (; argidx < SIZE(args); argidx++)
{