Eddie Hung
fffe42d4c1
cmp2lut: comment out unused since 362f4f9
2020-04-03 14:28:04 -07:00
whitequark
763401fc82
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
whitequark
ebee746ad2
ice40: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
...
IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Marcin Kościelnicki
0ed1062557
simcells.v: Generate the fine FF cell types by a python script.
...
This makes adding more FF types in the future much more manageable.
Fixes #1824 .
2020-04-02 18:37:15 +02:00
Eddie Hung
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
Alberto Gonzalez
fc6b898178
Fix indentation in techlibs/ice40/synth_ice40.cc.
2020-04-01 16:29:56 +00:00
David Shah
beab15b77c
Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix
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ice40: Map unmapped 'mince' DFFs to gate level
2020-03-21 17:35:27 +00:00
Sylvain Munaut
c15ce5a73e
ice40: Fix typos in SPRAM ABC9 timing specs
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-20 22:19:55 +01:00
David Shah
e813624f21
ice40: Map unmapped 'mince' DFFs to gate level
...
Signed-off-by: David Shah <dave@ds0.me>
2020-03-20 20:29:16 +00:00
Marcin Kościelnicki
9b982e929c
xilinx: Mark IOBUFDS.IOB as external pad
2020-03-20 14:37:38 +01:00
Sylvain Munaut
acd9eeef7c
ice40: Fix SPRAM model to keep data stable if chipselect is low
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According to the official simulation model, and also cross-checked
on real hardware, the data output of the SPRAM when chipselect is
low is kept stable. It doesn't go undefined.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-14 21:01:42 +01:00
Miodrag Milanovic
acb341745d
Fix invalid verilog syntax
2020-03-14 14:33:44 +01:00
N. Engelhardt
282d331e7e
Merge pull request #1716 from zeldin/ecp5_fix
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ecp5: remove unused parameter from \$__ECP5_PDPW16KD
2020-03-09 11:04:08 +01:00
N. Engelhardt
8a39a580e1
remove unused parameters
2020-03-06 16:45:36 +01:00
Eddie Hung
69f1555058
ice40: fix specify for ICE40_{LP,U}
2020-03-05 08:11:49 -08:00
Eddie Hung
0930c00f03
ice40: fix implicit signal in specify, also clamp negative times to 0
2020-03-04 15:28:17 -08:00
Eddie Hung
6eb528277e
Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1
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xilinx: cleanup DSP48E1 handling for abc9
2020-03-04 13:37:09 -08:00
Eddie Hung
7b543fdb0c
xilinx: consider DSP48E1.ADREG
2020-03-04 12:04:02 -08:00
Eddie Hung
512596760b
xilinx: cleanup DSP48E1 handling for abc9
2020-03-04 11:31:12 -08:00
Eddie Hung
f65fc845e5
xilinx: improve specify for DSP48E1
2020-03-04 11:31:12 -08:00
Eddie Hung
78d4fff69d
xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
2020-03-04 11:31:12 -08:00
N. Engelhardt
0ec971444b
Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc
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Add -flowmap option to `synth{,_ice40}`
2020-03-03 19:15:41 +01:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
R. Ou
7932672fc2
coolrunner2: Attempt to give wires/cells more meaningful names
2020-03-02 01:40:57 -08:00
R. Ou
b9c98e0100
coolrunner2: Fix invalid multiple fanouts of XOR/OR gates
...
In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:
module top(input a, input b, input clk_, output reg o, output o2);
wire clk;
BUFG bufg0 (
.I(clk_),
.O(clk),
);
always @(posedge clk)
o = a ^ b;
assign o2 = a ^ b;
endmodule
2020-03-02 01:07:15 -08:00
R. Ou
a618004897
coolrunner2: Fix packed register+input buffer insertion
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The register will be packed with the input buffer if and only if the
input buffer doesn't have any other loads.
2020-03-02 00:32:57 -08:00
R. Ou
a6aeee4e1a
coolrunner2: Insert many more required feedthrough cells
2020-03-01 16:56:21 -08:00
Dan Ravensloft
d7987fec12
Add -flowmap to synth and synth_ice40
2020-02-28 14:29:57 +00:00
Eddie Hung
090e54569a
Remove RAMB{18,36}E1 from cells_xtra.py
2020-02-27 10:33:04 -08:00
Eddie Hung
376319dc8d
xilinx: Update RAMB* specify entries
2020-02-27 10:17:29 -08:00
Eddie Hung
6bd9550100
ice40: add delays to SB_CARRY
2020-02-27 10:17:29 -08:00
Eddie Hung
3b74e0fa45
xilinx: add delays to INV
2020-02-27 10:17:29 -08:00
Eddie Hung
aa969f8778
More +/ice40/cells_sim.v fixes
2020-02-27 10:17:29 -08:00
Eddie Hung
b0ffd9cd8b
Make +/xilinx/cells_sim.v legal
2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
Eddie Hung
3ea5506f81
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
7d86aceee3
Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy
2020-02-27 10:17:29 -08:00
Eddie Hung
3728ef1765
ice40: fix specify for inverted clocks
2020-02-27 10:17:29 -08:00
Eddie Hung
aac309626b
Fix tests by gating some specify constructs from iverilog
2020-02-27 10:17:29 -08:00
Eddie Hung
e22fee6cdd
abc9_ops: ignore (* abc9_flop *) if not '-dff'
2020-02-27 10:17:29 -08:00
Eddie Hung
a76520112d
ice40: specify fixes
2020-02-27 10:17:29 -08:00
Eddie Hung
fb60d82971
ice40: move over to specify blocks for -abc9
2020-02-27 10:17:29 -08:00
Eddie Hung
a85c55113f
synth_ecp5: use +/abc9_model.v
2020-02-27 10:17:29 -08:00
Eddie Hung
8408c13405
Update xilinx for ABC9
2020-02-27 10:17:29 -08:00
Eddie Hung
ac24a23e31
Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
2020-02-27 10:17:29 -08:00
Eddie Hung
d2284715fa
ecp5: remove small LUT entries
2020-02-27 10:17:29 -08:00
Eddie Hung
ccc84f8923
Fix commented out specify statement
2020-02-27 10:17:29 -08:00
Eddie Hung
12d70ca8fb
xilinx: improve specify functionality
2020-02-27 10:17:29 -08:00
