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Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1
xilinx: cleanup DSP48E1 handling for abc9
This commit is contained in:
Eddie Hung
GitHub
commit
6eb528277e
4 changed files with 244 additions and 109 deletions
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@ -771,35 +771,16 @@ module DSP48E1 (
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.RSTM(RSTM),
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.RSTP(RSTP)
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);
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generate
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wire [29:0] $A;
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wire [17:0] $B;
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wire [47:0] $C;
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wire [24:0] $D;
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if (PREG == 0) begin
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if (MREG == 0 && AREG == 0) assign $A = A;
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else assign $A = 30'bx;
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if (MREG == 0 && BREG == 0) assign $B = B;
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else assign $B = 18'bx;
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if (MREG == 0 && DREG == 0) assign $D = D;
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else assign $D = 25'bx;
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if (CREG == 0) assign $C = C;
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else assign $C = 48'bx;
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end
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else begin
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assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx;
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end
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")
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$__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")
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$__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")
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$__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
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else
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$error("Invalid DSP48E1 configuration");
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endgenerate
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$__ABC9_DSP48E1 #(
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.ADREG(ADREG),
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.AREG(AREG),
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.BREG(BREG),
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.CREG(CREG),
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.DREG(DREG),
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.MREG(MREG),
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.PREG(PREG),
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.USE_DPORT(USE_DPORT),
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.USE_MULT(USE_MULT)
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) dsp_comb (
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.$A(A), .$B(B), .$C(C), .$D(D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
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endmodule
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@ -94,10 +94,9 @@ module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
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endspecify
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endmodule
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// Boxes used to represent the comb behaviour of various modes
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// of DSP48E1
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`define ABC9_DSP48E1(__NAME__) """
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module __NAME__ (
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// Boxes used to represent the comb behaviour of DSP48E1
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(* abc9_box *)
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module $__ABC9_DSP48E1 (
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input [29:0] $A,
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input [17:0] $B,
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input [47:0] $C,
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@ -106,44 +105,106 @@ module __NAME__ (
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input [47:0] $PCIN,
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input [47:0] $PCOUT,
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output [47:0] P,
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output [47:0] PCOUT);
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"""
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(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT)
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specify
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($A *> P) = 2823;
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($B *> P) = 2690;
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($C *> P) = 1325;
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($P *> P) = 0;
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($A *> PCOUT) = 2970;
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($B *> PCOUT) = 2838;
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($C *> PCOUT) = 1474;
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($PCOUT *> PCOUT) = 0;
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endspecify
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output [47:0] PCOUT
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);
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parameter integer ADREG = 1;
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parameter integer AREG = 1;
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parameter integer BREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer MREG = 1;
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parameter integer PREG = 1;
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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function integer \A.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
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end
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endfunction
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function integer \A.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
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end
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endfunction
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function integer \B.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
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end
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endfunction
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function integer \B.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
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end
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endfunction
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function integer \C.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
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end
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endfunction
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function integer \C.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
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end
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endfunction
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function integer \D.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
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end
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endfunction
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function integer \D.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
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end
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endfunction
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specify
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($P *> P) = 0;
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($PCOUT *> PCOUT) = 0;
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endspecify
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// Identical comb delays to DSP48E1 in cells_sim.v
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generate
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if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
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specify
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($A *> P) = \A.P.comb ();
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($A *> PCOUT) = \A.PCOUT.comb ();
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endspecify
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if (PREG == 0 && MREG == 0 && BREG == 0)
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specify
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($B *> P) = \B.P.comb ();
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($B *> PCOUT) = \B.PCOUT.comb ();
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endspecify
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if (PREG == 0 && CREG == 0)
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specify
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($C *> P) = \C.P.comb ();
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($C *> PCOUT) = \C.PCOUT.comb ();
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endspecify
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if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
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specify
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($D *> P) = \D.P.comb ();
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($D *> PCOUT) = \D.PCOUT.comb ();
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endspecify
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if (PREG == 0)
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specify
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($PCIN *> P) = 1107;
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($PCIN *> PCOUT) = 1255;
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endspecify
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endgenerate
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endmodule
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(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT_DPORT)
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specify
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($A *> P) = 3806;
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($B *> P) = 2690;
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($C *> P) = 1325;
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($D *> P) = 3700;
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($P *> P) = 0;
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($A *> PCOUT) = 3954;
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($B *> PCOUT) = 2838;
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($C *> PCOUT) = 1474;
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($D *> PCOUT) = 3700;
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($PCOUT *> PCOUT) = 0;
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endspecify
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endmodule
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(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1)
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specify
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($A *> P) = 1523;
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($B *> P) = 1509;
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($C *> P) = 1325;
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($P *> P) = 0;
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($A *> PCOUT) = 1671;
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($B *> PCOUT) = 1658;
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($C *> PCOUT) = 1474;
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($PCOUT *> PCOUT) = 0;
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endspecify
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endmodule
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`undef ABC9_DSP48E1
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@ -36,8 +36,7 @@ module $__ABC9_RAM7(input A, input [6:0] S, output Y);
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assign Y = A;
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endmodule
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(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *)
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module $ABC9_DSP48E1(
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module $__ABC9_DSP48E1(
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input [29:0] $A,
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input [17:0] $B,
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input [47:0] $C,
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@ -48,5 +47,15 @@ module $ABC9_DSP48E1(
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output [47:0] P,
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output [47:0] PCOUT
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);
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parameter integer ADREG = 1;
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parameter integer AREG = 1;
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parameter integer BREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer MREG = 1;
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parameter integer PREG = 1;
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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assign P = $P, PCOUT = $PCOUT;
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endmodule
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@ -3063,7 +3063,6 @@ module DSP48E1 (
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`ifdef YOSYS
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function integer \A.required ;
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begin
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\A.required = 0;
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if (AREG != 0) \A.required = 254;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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if (MREG != 0) \A.required = 1416;
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@ -3083,7 +3082,6 @@ module DSP48E1 (
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endfunction
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function integer \B.required ;
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begin
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\B.required = 0;
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if (BREG != 0) \B.required = 324;
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else if (MREG != 0) \B.required = 1285;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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@ -3099,14 +3097,12 @@ module DSP48E1 (
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endfunction
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function integer \C.required ;
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begin
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\C.required = 0;
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if (CREG != 0) \C.required = 168;
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else if (PREG != 0) \C.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1534 : 1244) ;
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end
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endfunction
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function integer \D.required ;
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begin
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\D.required = 0;
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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end
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
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@ -3119,15 +3115,8 @@ module DSP48E1 (
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end
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end
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endfunction
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function integer \PCIN.required ;
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begin
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\PCIN.required = 0;
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if (PREG != 0) \PCIN.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025) ;
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end
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endfunction
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function integer \P.arrival ;
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begin
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\P.arrival = 0;
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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if (PREG != 0) \P.arrival = 329;
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// Worst-case from CREG and MREG
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@ -3155,13 +3144,10 @@ module DSP48E1 (
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else if (AREG != 0) \P.arrival = 1632;
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else if (BREG != 0) \P.arrival = 1616;
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end
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//else
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// $error("Invalid DSP48E1 configuration");
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end
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endfunction
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function integer \PCOUT.arrival ;
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begin
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\PCOUT.arrival = 0;
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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if (PREG != 0) \PCOUT.arrival = 435;
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// Worst-case from CREG and MREG
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@ -3189,27 +3175,125 @@ module DSP48E1 (
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else if (AREG != 0) \PCOUT.arrival = 1780;
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else if (BREG != 0) \PCOUT.arrival = 1765;
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end
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//else
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// $error("Invalid DSP48E1 configuration");
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end
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endfunction
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function integer \A.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
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end
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endfunction
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function integer \A.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
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end
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endfunction
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function integer \B.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
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end
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endfunction
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function integer \B.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
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end
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endfunction
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function integer \C.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
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end
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endfunction
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function integer \C.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
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end
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endfunction
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function integer \D.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
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end
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endfunction
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function integer \D.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
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end
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endfunction
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specify
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$setup(A , posedge CLK &&& !IS_CLK_INVERTED, \A.required () );
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$setup(A , negedge CLK &&& IS_CLK_INVERTED, \A.required () );
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$setup(B , posedge CLK &&& !IS_CLK_INVERTED, \B.required () );
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$setup(B , negedge CLK &&& IS_CLK_INVERTED, \B.required () );
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$setup(C , posedge CLK &&& !IS_CLK_INVERTED, \C.required () );
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$setup(C , negedge CLK &&& IS_CLK_INVERTED, \C.required () );
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$setup(D , posedge CLK &&& !IS_CLK_INVERTED, \D.required () );
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$setup(D , negedge CLK &&& IS_CLK_INVERTED, \D.required () );
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$setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, \PCIN.required () );
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$setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, \PCIN.required () );
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if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ;
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if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ;
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if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
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if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
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endspecify
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generate
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if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
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specify
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(A *> P) = \A.P.comb ();
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(A *> PCOUT) = \A.PCOUT.comb ();
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endspecify
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else
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specify
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$setup(A, posedge CLK &&& !IS_CLK_INVERTED, \A.required () );
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$setup(A, negedge CLK &&& IS_CLK_INVERTED, \A.required () );
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endspecify
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if (PREG == 0 && MREG == 0 && BREG == 0)
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||||
specify
|
||||
(B *> P) = \B.P.comb ();
|
||||
(B *> PCOUT) = \B.PCOUT.comb ();
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
$setup(B, posedge CLK &&& !IS_CLK_INVERTED, \B.required () );
|
||||
$setup(B, negedge CLK &&& IS_CLK_INVERTED, \B.required () );
|
||||
endspecify
|
||||
|
||||
if (PREG == 0 && CREG == 0)
|
||||
specify
|
||||
(C *> P) = \C.P.comb ();
|
||||
(C *> PCOUT) = \C.PCOUT.comb ();
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
$setup(C, posedge CLK &&& !IS_CLK_INVERTED, \C.required () );
|
||||
$setup(C, negedge CLK &&& IS_CLK_INVERTED, \C.required () );
|
||||
endspecify
|
||||
|
||||
if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
|
||||
specify
|
||||
(D *> P) = \D.P.comb ();
|
||||
(D *> PCOUT) = \D.PCOUT.comb ();
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
$setup(D, posedge CLK &&& !IS_CLK_INVERTED, \D.required () );
|
||||
$setup(D, negedge CLK &&& IS_CLK_INVERTED, \D.required () );
|
||||
endspecify
|
||||
|
||||
if (PREG == 0)
|
||||
specify
|
||||
(PCIN *> P) = 1107;
|
||||
(PCIN *> PCOUT) = 1255;
|
||||
endspecify
|
||||
else
|
||||
specify
|
||||
$setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025);
|
||||
$setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025);
|
||||
endspecify
|
||||
|
||||
if (PREG || AREG || ADREG || BREG || CREG || DREG || MREG)
|
||||
specify
|
||||
if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ;
|
||||
if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ;
|
||||
if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
|
||||
if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
|
||||
endspecify
|
||||
endgenerate
|
||||
`endif
|
||||
|
||||
initial begin
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue