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yosys/techlibs
2020-03-04 11:31:12 -08:00
..
achronix Remove executable flag from files 2020-02-15 10:36:44 +01:00
anlogic synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
common Create +/abc9_model.v for $__ABC9_{DELAY,FF_} 2020-02-27 10:17:29 -08:00
coolrunner2 coolrunner2: Attempt to give wires/cells more meaningful names 2020-03-02 01:40:57 -08:00
easic
ecp5 synth_ecp5: use +/abc9_model.v 2020-02-27 10:17:29 -08:00
efinix synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
gowin Removing cells_sim.v from bram techmap pass 2020-02-06 14:38:29 -06:00
greenpak4 synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
ice40 ice40: add delays to SB_CARRY 2020-02-27 10:17:29 -08:00
intel
sf2 synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
xilinx xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v 2020-03-04 11:31:12 -08:00
.gitignore