mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-08 10:25:19 +00:00
b9c98e0100
In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:
module top(input a, input b, input clk_, output reg o, output o2);
wire clk;
BUFG bufg0 (
.I(clk_),
.O(clk),
);
always @(posedge clk)
o = a ^ b;
assign o2 = a ^ b;
endmodule
|
||
|---|---|---|
| .. | ||
| achronix | ||
| anlogic | ||
| common | ||
| coolrunner2 | ||
| easic | ||
| ecp5 | ||
| efinix | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||