mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

kernel: big fat patch to use more ID::*, otherwise ID(*)

Browse source
This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
Download patch file Download diff file Expand all files Collapse all files

24
techlibs/anlogic/anlogic_eqn.cc
View file

@ -74,34 +74,34 @@ struct AnlogicEqnPass : public Pass {
{
for (auto cell : module->selected_cells())
{
if (cell->type == "\\AL_MAP_LUT1")
if (cell->type == ID(AL_MAP_LUT1))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),1));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),1));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT2")
if (cell->type == ID(AL_MAP_LUT2))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),2));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),2));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT3")
if (cell->type == ID(AL_MAP_LUT3))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),3));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),3));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT4")
if (cell->type == ID(AL_MAP_LUT4))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),4));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),4));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT5")
if (cell->type == ID(AL_MAP_LUT5))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),5));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),5));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT6")
if (cell->type == ID(AL_MAP_LUT6))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),6));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),6));
cnt++;
}
}

38
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -39,13 +39,13 @@ static void fix_carry_chain(Module *module)
for (auto cell : module->cells())
{
if (cell->type == "\\AL_MAP_ADDER") {
if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
if (cell->type == ID(AL_MAP_ADDER)) {
if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue;
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
if (bit_i0 == State::S0 && bit_i1== State::S0) {
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
SigSpec o = cell->getPort("\\o");
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigSpec o = cell->getPort(ID(o));
if (GetSize(o) == 2) {
SigBit bit_o = o[0];
ci_bits.insert(bit_ci);
@ -57,11 +57,11 @@ static void fix_carry_chain(Module *module)
vector<Cell*> adders_to_fix_cells;
for (auto cell : module->cells())
{
if (cell->type == "\\AL_MAP_ADDER") {
if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
if (cell->type == ID(AL_MAP_ADDER)) {
if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue;
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
@ -75,23 +75,23 @@ static void fix_carry_chain(Module *module)
for (auto cell : adders_to_fix_cells)
{
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
Cell *c = module->addCell(NEW_ID, "\\AL_MAP_ADDER");
Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEW_ID);
SigBit dummy_bit = module->addWire(NEW_ID);
SigSpec bits;
bits.append(dummy_bit);
bits.append(new_bit);
c->setParam("\\ALUTYPE", Const("ADD_CARRY"));
c->setPort("\\a", bit);
c->setPort("\\b", State::S0);
c->setPort("\\c", State::S0);
c->setPort("\\o", bits);
c->setParam(ID(ALUTYPE), Const("ADD_CARRY"));
c->setPort(ID(a), bit);
c->setPort(ID(b), State::S0);
c->setPort(ID(c), State::S0);
c->setPort(ID(o), bits);
cell->setPort("\\c", new_bit);
cell->setPort(ID(c), new_bit);
}
}

166
techlibs/coolrunner2/coolrunner2_fixup.cc
View file

@ -34,9 +34,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", true);
xor_cell->setPort("\\OUT", outwire);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), true);
xor_cell->setPort(ID(OUT), outwire);
}
else if (inwire == SigBit(false))
{
@ -45,9 +45,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\OUT", outwire);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(OUT), outwire);
}
else if (inwire == SigBit(RTLIL::State::Sx))
{
@ -57,9 +57,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\OUT", outwire);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(OUT), outwire);
}
else
{
@ -73,19 +73,19 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", and_to_xor_wire);
and_cell->setPort("\\IN", inwire);
and_cell->setPort("\\IN_B", SigSpec());
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), 1);
and_cell->setParam(ID(COMP_INP), 0);
and_cell->setPort(ID(OUT), and_to_xor_wire);
and_cell->setPort(ID(IN), inwire);
and_cell->setPort(ID(IN_B), SigSpec());
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", outwire);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(IN_PTC), and_to_xor_wire);
xor_cell->setPort(ID(OUT), outwire);
}
return outwire;
@ -100,12 +100,12 @@ RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", outwire);
and_cell->setPort("\\IN", inwire);
and_cell->setPort("\\IN_B", SigSpec());
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), 1);
and_cell->setParam(ID(COMP_INP), 0);
and_cell->setPort(ID(OUT), outwire);
and_cell->setPort(ID(IN), inwire);
and_cell->setPort(ID(IN_B), SigSpec());
return outwire;
}
@ -133,10 +133,10 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_ff;
for (auto cell : module->selected_cells())
{
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
auto output = sigmap(cell->getPort("\\Q")[0]);
auto output = sigmap(cell->getPort(ID::Q)[0]);
sig_fed_by_ff.insert(output);
}
}
@ -145,9 +145,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_xor;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\MACROCELL_XOR")
if (cell->type == ID(MACROCELL_XOR))
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
auto output = sigmap(cell->getPort(ID(OUT))[0]);
sig_fed_by_xor.insert(output);
}
}
@ -156,10 +156,10 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_io;
for (auto cell : module->selected_cells())
{
if (cell->type.in("\\IBUF", "\\IOBUFE"))
if (cell->type.in(ID(IBUF), ID(IOBUFE)))
{
if (cell->hasPort("\\O")) {
auto output = sigmap(cell->getPort("\\O")[0]);
if (cell->hasPort(ID::O)) {
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_io.insert(output);
}
}
@ -169,9 +169,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_pterm;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ANDTERM")
if (cell->type == ID(ANDTERM))
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
auto output = sigmap(cell->getPort(ID(OUT))[0]);
sig_fed_by_pterm.insert(output);
}
}
@ -180,9 +180,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_bufg;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFG")
if (cell->type == ID(BUFG))
{
auto output = sigmap(cell->getPort("\\O")[0]);
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufg.insert(output);
}
}
@ -191,9 +191,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_bufgsr;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFGSR")
if (cell->type == ID(BUFGSR))
{
auto output = sigmap(cell->getPort("\\O")[0]);
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufgsr.insert(output);
}
}
@ -202,9 +202,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_bufgts;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFGTS")
if (cell->type == ID(BUFGTS))
{
auto output = sigmap(cell->getPort("\\O")[0]);
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufgts.insert(output);
}
}
@ -213,9 +213,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_ibuf;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\IBUF")
if (cell->type == ID(IBUF))
{
auto output = sigmap(cell->getPort("\\O")[0]);
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_ibuf.insert(output);
}
}
@ -254,15 +254,15 @@ struct Coolrunner2FixupPass : public Pass {
// the pad-to-zia path has to be used up and the register
// can't be packed with the ibuf.
if (fanout_count == 1 && maybe_ff_cell->type.in(
"\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
SigBit input;
if (maybe_ff_cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
input = sigmap(maybe_ff_cell->getPort("\\T")[0]);
if (maybe_ff_cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
input = sigmap(maybe_ff_cell->getPort(ID::T)[0]);
else
input = sigmap(maybe_ff_cell->getPort("\\D")[0]);
SigBit output = sigmap(maybe_ff_cell->getPort("\\Q")[0]);
input = sigmap(maybe_ff_cell->getPort(ID::D)[0]);
SigBit output = sigmap(maybe_ff_cell->getPort(ID::Q)[0]);
if (input == ibuf_out_wire)
{
@ -279,17 +279,17 @@ struct Coolrunner2FixupPass : public Pass {
for (auto cell : module->selected_cells())
{
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
// Buffering FF inputs. FF inputs can only come from either
// an IO pin or from an XOR. Otherwise AND/XOR cells need
// to be inserted.
SigBit input;
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
input = sigmap(cell->getPort("\\T")[0]);
if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
input = sigmap(cell->getPort(ID::T)[0]);
else
input = sigmap(cell->getPort("\\D")[0]);
input = sigmap(cell->getPort(ID::D)[0]);
// If the input wasn't an XOR nor an IO, then a buffer
// definitely needs to be added.
@ -302,10 +302,10 @@ struct Coolrunner2FixupPass : public Pass {
auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str());
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
cell->setPort("\\T", xor_to_ff_wire);
if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
cell->setPort(ID::T, xor_to_ff_wire);
else
cell->setPort("\\D", xor_to_ff_wire);
cell->setPort(ID::D, xor_to_ff_wire);
}
// Buffering FF clocks. FF clocks can only come from either
@ -313,10 +313,10 @@ struct Coolrunner2FixupPass : public Pass {
// in coolrunner2_sop (e.g. if clock is generated from
// AND-ing two signals) but not in all cases.
SigBit clock;
if (cell->type.in("\\LDCP", "\\LDCP_N"))
clock = sigmap(cell->getPort("\\G")[0]);
if (cell->type.in(ID(LDCP), ID(LDCP_N)))
clock = sigmap(cell->getPort(ID::G)[0]);
else
clock = sigmap(cell->getPort("\\C")[0]);
clock = sigmap(cell->getPort(ID::C)[0]);
if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock])
{
@ -324,16 +324,16 @@ struct Coolrunner2FixupPass : public Pass {
auto pterm_to_ff_wire = makeptermbuffer(module, clock);
if (cell->type.in("\\LDCP", "\\LDCP_N"))
cell->setPort("\\G", pterm_to_ff_wire);
if (cell->type.in(ID(LDCP), ID(LDCP_N)))
cell->setPort(ID::G, pterm_to_ff_wire);
else
cell->setPort("\\C", pterm_to_ff_wire);
cell->setPort(ID::C, pterm_to_ff_wire);
}
// Buffering FF set/reset. This can only come from either
// a pterm or a bufgsr.
SigBit set;
set = sigmap(cell->getPort("\\PRE")[0]);
set = sigmap(cell->getPort(ID(PRE))[0]);
if (set != SigBit(false))
{
if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set])
@ -342,12 +342,12 @@ struct Coolrunner2FixupPass : public Pass {
auto pterm_to_ff_wire = makeptermbuffer(module, set);
cell->setPort("\\PRE", pterm_to_ff_wire);
cell->setPort(ID(PRE), pterm_to_ff_wire);
}
}
SigBit reset;
reset = sigmap(cell->getPort("\\CLR")[0]);
reset = sigmap(cell->getPort(ID::CLR)[0]);
if (reset != SigBit(false))
{
if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset])
@ -356,24 +356,24 @@ struct Coolrunner2FixupPass : public Pass {
auto pterm_to_ff_wire = makeptermbuffer(module, reset);
cell->setPort("\\CLR", pterm_to_ff_wire);
cell->setPort(ID::CLR, pterm_to_ff_wire);
}
}
// Buffering FF clock enable
// FIXME: This doesn't fully fix PTC conflicts
// FIXME: Need to ensure constant enables are optimized out
if (cell->type.in("\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
if (cell->type.in(ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
SigBit ce;
ce = sigmap(cell->getPort("\\CE")[0]);
ce = sigmap(cell->getPort(ID(CE))[0]);
if (!sig_fed_by_pterm[ce])
{
log("Buffering clock enable to \"%s\"\n", cell->name.c_str());
auto pterm_to_ff_wire = makeptermbuffer(module, ce);
cell->setPort("\\CE", pterm_to_ff_wire);
cell->setPort(ID(CE), pterm_to_ff_wire);
}
}
}
@ -381,10 +381,10 @@ struct Coolrunner2FixupPass : public Pass {
for (auto cell : module->selected_cells())
{
if (cell->type == "\\IOBUFE")
if (cell->type == ID(IOBUFE))
{
// Buffer IOBUFE inputs. This can only be fed from an XOR or FF.
SigBit input = sigmap(cell->getPort("\\I")[0]);
SigBit input = sigmap(cell->getPort(ID::I)[0]);
if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) ||
packed_reg_out[input])
@ -393,22 +393,22 @@ struct Coolrunner2FixupPass : public Pass {
auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str());
cell->setPort("\\I", xor_to_io_wire);
cell->setPort(ID::I, xor_to_io_wire);
}
// Buffer IOBUFE enables. This can only be fed from a pterm
// or a bufgts.
if (cell->hasPort("\\E"))
if (cell->hasPort(ID::E))
{
SigBit oe;
oe = sigmap(cell->getPort("\\E")[0]);
oe = sigmap(cell->getPort(ID::E)[0]);
if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe])
{
log("Buffering output enable to \"%s\"\n", cell->name.c_str());
auto pterm_to_oe_wire = makeptermbuffer(module, oe);
cell->setPort("\\E", pterm_to_oe_wire);
cell->setPort(ID::E, pterm_to_oe_wire);
}
}
}
@ -422,9 +422,9 @@ struct Coolrunner2FixupPass : public Pass {
dict<SigBit, RTLIL::Cell *> xor_out_to_xor_cell;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\MACROCELL_XOR")
if (cell->type == ID(MACROCELL_XOR))
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
auto output = sigmap(cell->getPort(ID(OUT))[0]);
xor_out_to_xor_cell[output] = cell;
}
}
@ -433,7 +433,7 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> xor_fanout_once;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ANDTERM")
if (cell->type == ID(ANDTERM))
continue;
for (auto &conn : cell->connections())
@ -456,7 +456,7 @@ struct Coolrunner2FixupPass : public Pass {
module->uniquify(xor_cell->name), xor_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
new_xor_cell->setPort("\\OUT", new_wire);
new_xor_cell->setPort(ID(OUT), new_wire);
cell->setPort(conn.first, new_wire);
}
xor_fanout_once.insert(wire_in);
@ -473,9 +473,9 @@ struct Coolrunner2FixupPass : public Pass {
dict<SigBit, RTLIL::Cell *> or_out_to_or_cell;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ORTERM")
if (cell->type == ID(ORTERM))
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
auto output = sigmap(cell->getPort(ID(OUT))[0]);
or_out_to_or_cell[output] = cell;
}
}
@ -504,7 +504,7 @@ struct Coolrunner2FixupPass : public Pass {
module->uniquify(or_cell->name), or_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
new_or_cell->setPort("\\OUT", new_wire);
new_or_cell->setPort(ID(OUT), new_wire);
cell->setPort(conn.first, new_wire);
}
or_fanout_once.insert(wire_in);

102
techlibs/coolrunner2/coolrunner2_sop.cc
View file

@ -47,7 +47,7 @@ struct Coolrunner2SopPass : public Pass {
dict<SigBit, tuple<SigBit, Cell*>> not_cells;
for (auto cell : module->selected_cells())
{
if (cell->type == "$_NOT_")
if (cell->type == ID($_NOT_))
{
auto not_input = sigmap(cell->getPort(ID::A)[0]);
auto not_output = sigmap(cell->getPort(ID::Y)[0]);
@ -56,43 +56,43 @@ struct Coolrunner2SopPass : public Pass {
}
// Find wires that need to become special product terms
dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_no_inv;
dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_no_inv;
dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_inv;
for (auto cell : module->selected_cells())
{
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
"\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP),
ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N)))
{
if (cell->hasPort("\\PRE"))
special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
tuple<Cell*, const char *>(cell, "\\PRE"));
if (cell->hasPort("\\CLR"))
special_pterms_no_inv[sigmap(cell->getPort("\\CLR")[0])].insert(
tuple<Cell*, const char *>(cell, "\\CLR"));
if (cell->hasPort("\\CE"))
special_pterms_no_inv[sigmap(cell->getPort("\\CE")[0])].insert(
tuple<Cell*, const char *>(cell, "\\CE"));
if (cell->hasPort(ID(PRE)))
special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert(
make_tuple(cell, ID(PRE)));
if (cell->hasPort(ID::CLR))
special_pterms_no_inv[sigmap(cell->getPort(ID::CLR)[0])].insert(
make_tuple(cell, ID::CLR));
if (cell->hasPort(ID(CE)))
special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert(
make_tuple(cell, ID(CE)));
if (cell->hasPort("\\C"))
special_pterms_inv[sigmap(cell->getPort("\\C")[0])].insert(
tuple<Cell*, const char *>(cell, "\\C"));
if (cell->hasPort("\\G"))
special_pterms_inv[sigmap(cell->getPort("\\G")[0])].insert(
tuple<Cell*, const char *>(cell, "\\G"));
if (cell->hasPort(ID::C))
special_pterms_inv[sigmap(cell->getPort(ID::C)[0])].insert(
make_tuple(cell, ID::C));
if (cell->hasPort(ID::G))
special_pterms_inv[sigmap(cell->getPort(ID::G)[0])].insert(
make_tuple(cell, ID::G));
}
}
// Process $sop cells
for (auto cell : module->selected_cells())
{
if (cell->type == "$sop")
if (cell->type == ID($sop))
{
// Read the inputs/outputs/parameters of the $sop cell
auto sop_inputs = sigmap(cell->getPort(ID::A));
auto sop_output = sigmap(cell->getPort(ID::Y))[0];
auto sop_depth = cell->getParam("\\DEPTH").as_int();
auto sop_width = cell->getParam("\\WIDTH").as_int();
auto sop_table = cell->getParam("\\TABLE");
auto sop_depth = cell->getParam(ID::DEPTH).as_int();
auto sop_width = cell->getParam(ID::WIDTH).as_int();
auto sop_table = cell->getParam(ID::TABLE);
auto sop_output_wire_name = sop_output.wire->name.c_str();
@ -139,12 +139,12 @@ struct Coolrunner2SopPass : public Pass {
// Construct the cell
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", GetSize(and_in_true));
and_cell->setParam("\\COMP_INP", GetSize(and_in_comp));
and_cell->setPort("\\OUT", and_out);
and_cell->setPort("\\IN", and_in_true);
and_cell->setPort("\\IN_B", and_in_comp);
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), GetSize(and_in_true));
and_cell->setParam(ID(COMP_INP), GetSize(and_in_comp));
and_cell->setPort(ID(OUT), and_out);
and_cell->setPort(ID(IN), and_in_true);
and_cell->setPort(ID(IN_B), and_in_comp);
}
if (sop_depth == 1)
@ -152,17 +152,17 @@ struct Coolrunner2SopPass : public Pass {
// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
xor_cell->setPort("\\OUT", sop_output);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), has_invert);
xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin());
xor_cell->setPort(ID(OUT), sop_output);
// Special P-term handling
if (is_special_pterm)
{
// Can always connect the P-term directly if it's going
// into something invert-capable
for (auto x : special_pterms_inv[sop_output])
for (const auto &x : special_pterms_inv[sop_output])
{
std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
@ -170,14 +170,14 @@ struct Coolrunner2SopPass : public Pass {
if (has_invert)
{
auto cell = std::get<0>(x);
if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
if (cell->type == ID(FDCP)) cell->type = ID(FDCP_N);
else if (cell->type == ID(FDCP_N)) cell->type = ID(FDCP);
else if (cell->type == ID(FTCP)) cell->type = ID(FTCP_N);
else if (cell->type == ID(FTCP_N)) cell->type = ID(FTCP);
else if (cell->type == ID(FDCPE)) cell->type = ID(FDCPE_N);
else if (cell->type == ID(FDCPE_N)) cell->type = ID(FDCPE);
else if (cell->type == ID(LDCP)) cell->type = ID(LDCP_N);
else if (cell->type == ID(LDCP_N)) cell->type = ID(LDCP);
else log_assert(!"Internal error! Bad cell type!");
}
}
@ -203,18 +203,18 @@ struct Coolrunner2SopPass : public Pass {
// Construct the OR cell
auto or_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)),
"\\ORTERM");
or_cell->setParam("\\WIDTH", sop_depth);
or_cell->setPort("\\IN", intermed_wires);
or_cell->setPort("\\OUT", or_to_xor_wire);
ID(ORTERM));
or_cell->setParam(ID::WIDTH, sop_depth);
or_cell->setPort(ID(IN), intermed_wires);
or_cell->setPort(ID(OUT), or_to_xor_wire);
// Construct the XOR cell
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
xor_cell->setPort("\\OUT", sop_output);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), has_invert);
xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire);
xor_cell->setPort(ID(OUT), sop_output);
}
// Finally, remove the $sop cell

44
techlibs/ecp5/ecp5_ffinit.cc
View file

@ -63,11 +63,11 @@ struct Ecp5FfinitPass : public Pass {
for (auto wire : module->selected_wires())
{
if (wire->attributes.count("\\init") == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
Const initval = wire->attributes.at("\\init");
Const initval = wire->attributes.at(ID::init);
init_wires.insert(wire);
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
@ -94,11 +94,11 @@ struct Ecp5FfinitPass : public Pass {
}
for (auto cell : module->selected_cells())
{
if (cell->type != "\\TRELLIS_FF")
if (cell->type != ID(TRELLIS_FF))
continue;
SigSpec sig_d = cell->getPort("\\DI");
SigSpec sig_q = cell->getPort("\\Q");
SigSpec sig_lsr = cell->getPort("\\LSR");
SigSpec sig_d = cell->getPort(ID(DI));
SigSpec sig_q = cell->getPort(ID::Q);
SigSpec sig_lsr = cell->getPort(ID(LSR));
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
@ -107,8 +107,8 @@ struct Ecp5FfinitPass : public Pass {
SigBit bit_q = sigmap(sig_q[0]);
std::string regset = "RESET";
if (cell->hasParam("\\REGSET"))
regset = cell->getParam("\\REGSET").decode_string();
if (cell->hasParam(ID(REGSET)))
regset = cell->getParam(ID(REGSET)).decode_string();
State resetState;
if (regset == "SET")
resetState = State::S1;
@ -136,8 +136,8 @@ struct Ecp5FfinitPass : public Pass {
if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
std::string srmode = "LSR_OVER_CE";
if (cell->hasParam("\\SRMODE"))
srmode = cell->getParam("\\SRMODE").decode_string();
if (cell->hasParam(ID(SRMODE)))
srmode = cell->getParam(ID(SRMODE)).decode_string();
if (srmode == "ASYNC") {
log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
@ -150,14 +150,14 @@ struct Ecp5FfinitPass : public Pass {
module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
}
cell->setPort("\\DI", new_bit_d);
cell->setPort("\\LSR", State::S0);
cell->setPort(ID(DI), new_bit_d);
cell->setPort(ID(LSR), State::S0);
if(cell->hasPort("\\CE")) {
if(cell->hasPort(ID(CE))) {
std::string cemux = "CE";
if (cell->hasParam("\\CEMUX"))
cemux = cell->getParam("\\CEMUX").decode_string();
SigSpec sig_ce = cell->getPort("\\CE");
if (cell->hasParam(ID(CEMUX)))
cemux = cell->getParam(ID(CEMUX)).decode_string();
SigSpec sig_ce = cell->getPort(ID(CE));
if (GetSize(sig_ce) >= 1) {
SigBit bit_ce = sigmap(sig_ce[0]);
Wire *new_bit_ce = module->addWire(NEW_ID);
@ -165,25 +165,25 @@ struct Ecp5FfinitPass : public Pass {
module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
else
module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
cell->setPort("\\CE", new_bit_ce);
cell->setPort(ID(CE), new_bit_ce);
}
}
cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
handled_initbits.insert(bit_q);
}
} else {
cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
handled_initbits.insert(bit_q);
}
}
for (auto wire : init_wires)
{
if (wire->attributes.count("\\init") == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
Const &initval = wire->attributes.at("\\init");
Const &initval = wire->attributes.at(ID::init);
bool remove_attribute = true;
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
@ -194,7 +194,7 @@ struct Ecp5FfinitPass : public Pass {
}
if (remove_attribute)
wire->attributes.erase("\\init");
wire->attributes.erase(ID::init);
}
}
}

4
techlibs/ecp5/ecp5_gsr.cc
View file

@ -85,7 +85,7 @@ struct Ecp5GsrPass : public Pass {
continue;
bool gsren = found_gsr;
if (cell->get_bool_attribute("\\nogsr"))
if (cell->get_bool_attribute(ID(nogsr)))
gsren = false;
cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
@ -102,7 +102,7 @@ struct Ecp5GsrPass : public Pass {
{
if (cell->type != ID($_NOT_))
continue;
SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y));
SigSpec sig_a = cell->getPort(ID::A), sig_y = cell->getPort(ID::Y);
if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
continue;
SigBit a = sigmap(sig_a[0]);

38
techlibs/efinix/efinix_fixcarry.cc
View file

@ -39,12 +39,12 @@ static void fix_carry_chain(Module *module)
for (auto cell : module->cells())
{
if (cell->type == "\\EFX_ADD") {
SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
if (cell->type == ID(EFX_ADD)) {
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
if (bit_i0 == State::S0 && bit_i1== State::S0) {
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
SigBit bit_o = sigmap(cell->getPort("\\O"));
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit bit_o = sigmap(cell->getPort(ID::O));
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
}
@ -54,10 +54,10 @@ static void fix_carry_chain(Module *module)
vector<Cell*> adders_to_fix_cells;
for (auto cell : module->cells())
{
if (cell->type == "\\EFX_ADD") {
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
if (cell->type == ID(EFX_ADD)) {
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
@ -71,20 +71,20 @@ static void fix_carry_chain(Module *module)
for (auto cell : adders_to_fix_cells)
{
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
Cell *c = module->addCell(NEW_ID, "\\EFX_ADD");
Cell *c = module->addCell(NEW_ID, ID(EFX_ADD));
SigBit new_bit = module->addWire(NEW_ID);
c->setParam("\\I0_POLARITY", State::S1);
c->setParam("\\I1_POLARITY", State::S1);
c->setPort("\\I0", bit);
c->setPort("\\I1", State::S1);
c->setPort("\\CI", State::S0);
c->setPort("\\CO", new_bit);
c->setParam(ID(I0_POLARITY), State::S1);
c->setParam(ID(I1_POLARITY), State::S1);
c->setPort(ID(I0), bit);
c->setPort(ID(I1), State::S1);
c->setPort(ID::CI, State::S0);
c->setPort(ID::CO, new_bit);
cell->setPort("\\CI", new_bit);
cell->setPort(ID::CI, new_bit);
}
}
@ -101,7 +101,7 @@ struct EfinixCarryFixPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing efinix_fixcarry pass (fix invalid carry chain).\n");
log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

20
techlibs/efinix/efinix_gbuf.cc
View file

@ -34,14 +34,14 @@ static void handle_gbufs(Module *module)
for (auto cell : module->cells())
{
if (cell->type == "\\EFX_FF") {
for (auto bit : sigmap(cell->getPort("\\CLK")))
if (cell->type == ID(EFX_FF)) {
for (auto bit : sigmap(cell->getPort(ID::CLK)))
clk_bits.insert(bit);
}
if (cell->type == "\\EFX_RAM_5K") {
for (auto bit : sigmap(cell->getPort("\\RCLK")))
if (cell->type == ID(EFX_RAM_5K)) {
for (auto bit : sigmap(cell->getPort(ID(RCLK))))
clk_bits.insert(bit);
for (auto bit : sigmap(cell->getPort("\\WCLK")))
for (auto bit : sigmap(cell->getPort(ID(WCLK))))
clk_bits.insert(bit);
}
}
@ -59,11 +59,11 @@ static void handle_gbufs(Module *module)
if (!clk_bits.count(canonical_bit))
continue;
Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE");
Cell *c = module->addCell(NEW_ID, ID(EFX_GBUFCE));
SigBit new_bit = module->addWire(NEW_ID);
c->setParam("\\CE_POLARITY", State::S1);
c->setPort("\\O", new_bit);
c->setPort("\\CE", State::S1);
c->setParam(ID(CE_POLARITY), State::S1);
c->setPort(ID::O, new_bit);
c->setPort(ID(CE), State::S1);
pad_bits.push_back(make_pair(c, bit));
rewrite_bits[canonical_bit] = new_bit;
@ -82,7 +82,7 @@ static void handle_gbufs(Module *module)
module->rewrite_sigspecs(rewrite_function);
for (auto &it : pad_bits)
it.first->setPort("\\I", it.second);
it.first->setPort(ID::I, it.second);
}
struct EfinixGbufPass : public Pass {

10
techlibs/gowin/determine_init.cc
View file

@ -55,12 +55,12 @@ struct DetermineInitPass : public Pass {
{
for (auto cell : module->selected_cells())
{
if (cell->type == "\\RAM16S4")
if (cell->type == ID(RAM16S4))
{
cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0")));
cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1")));
cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2")));
cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3")));
cell->setParam(ID(INIT_0), determine_init(cell->getParam(ID(INIT_0))));
cell->setParam(ID(INIT_1), determine_init(cell->getParam(ID(INIT_1))));
cell->setParam(ID(INIT_2), determine_init(cell->getParam(ID(INIT_2))));
cell->setParam(ID(INIT_3), determine_init(cell->getParam(ID(INIT_3))));
cnt++;
}
}

74
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -33,37 +33,37 @@ void invert_gp_dff(Cell *cell, bool invert_input)
if (!invert_input)
{
Const initval = cell->getParam("\\INIT");
Const initval = cell->getParam(ID::INIT);
if (GetSize(initval) >= 1) {
if (initval.bits[0] == State::S0)
initval.bits[0] = State::S1;
else if (initval.bits[0] == State::S1)
initval.bits[0] = State::S0;
cell->setParam("\\INIT", initval);
cell->setParam(ID::INIT, initval);
}
if (cell_type_r && cell_type_s)
{
Const srmode = cell->getParam("\\SRMODE");
Const srmode = cell->getParam(ID(SRMODE));
if (GetSize(srmode) >= 1) {
if (srmode.bits[0] == State::S0)
srmode.bits[0] = State::S1;
else if (srmode.bits[0] == State::S1)
srmode.bits[0] = State::S0;
cell->setParam("\\SRMODE", srmode);
cell->setParam(ID(SRMODE), srmode);
}
}
else
{
if (cell_type_r) {
cell->setPort("\\nSET", cell->getPort("\\nRST"));
cell->unsetPort("\\nRST");
cell->setPort(ID(nSET), cell->getPort(ID(nRST)));
cell->unsetPort(ID(nRST));
cell_type_r = false;
cell_type_s = true;
} else
if (cell_type_s) {
cell->setPort("\\nRST", cell->getPort("\\nSET"));
cell->unsetPort("\\nSET");
cell->setPort(ID(nRST), cell->getPort(ID(nSET)));
cell->unsetPort(ID(nSET));
cell_type_r = true;
cell_type_s = false;
}
@ -71,12 +71,12 @@ void invert_gp_dff(Cell *cell, bool invert_input)
}
if (cell_type_i) {
cell->setPort("\\Q", cell->getPort("\\nQ"));
cell->unsetPort("\\nQ");
cell->setPort(ID::Q, cell->getPort(ID(nQ)));
cell->unsetPort(ID(nQ));
cell_type_i = false;
} else {
cell->setPort("\\nQ", cell->getPort("\\Q"));
cell->unsetPort("\\Q");
cell->setPort(ID(nQ), cell->getPort(ID::Q));
cell->unsetPort(ID::Q);
cell_type_i = true;
}
@ -115,23 +115,23 @@ struct Greenpak4DffInvPass : public Pass {
extra_args(args, argidx, design);
pool<IdString> gp_dff_types;
gp_dff_types.insert("\\GP_DFF");
gp_dff_types.insert("\\GP_DFFI");
gp_dff_types.insert("\\GP_DFFR");
gp_dff_types.insert("\\GP_DFFRI");
gp_dff_types.insert("\\GP_DFFS");
gp_dff_types.insert("\\GP_DFFSI");
gp_dff_types.insert("\\GP_DFFSR");
gp_dff_types.insert("\\GP_DFFSRI");
gp_dff_types.insert(ID(GP_DFF));
gp_dff_types.insert(ID(GP_DFFI));
gp_dff_types.insert(ID(GP_DFFR));
gp_dff_types.insert(ID(GP_DFFRI));
gp_dff_types.insert(ID(GP_DFFS));
gp_dff_types.insert(ID(GP_DFFSI));
gp_dff_types.insert(ID(GP_DFFSR));
gp_dff_types.insert(ID(GP_DFFSRI));
gp_dff_types.insert("\\GP_DLATCH");
gp_dff_types.insert("\\GP_DLATCHI");
gp_dff_types.insert("\\GP_DLATCHR");
gp_dff_types.insert("\\GP_DLATCHRI");
gp_dff_types.insert("\\GP_DLATCHS");
gp_dff_types.insert("\\GP_DLATCHSI");
gp_dff_types.insert("\\GP_DLATCHSR");
gp_dff_types.insert("\\GP_DLATCHSRI");
gp_dff_types.insert(ID(GP_DLATCH));
gp_dff_types.insert(ID(GP_DLATCHI));
gp_dff_types.insert(ID(GP_DLATCHR));
gp_dff_types.insert(ID(GP_DLATCHRI));
gp_dff_types.insert(ID(GP_DLATCHS));
gp_dff_types.insert(ID(GP_DLATCHSI));
gp_dff_types.insert(ID(GP_DLATCHSR));
gp_dff_types.insert(ID(GP_DLATCHSRI));
for (auto module : design->selected_modules())
{
@ -163,9 +163,9 @@ struct Greenpak4DffInvPass : public Pass {
continue;
}
if (cell->type == "\\GP_INV") {
SigBit in_bit = sigmap(cell->getPort("\\IN"));
SigBit out_bit = sigmap(cell->getPort("\\OUT"));
if (cell->type == ID(GP_INV)) {
SigBit in_bit = sigmap(cell->getPort(ID(IN)));
SigBit out_bit = sigmap(cell->getPort(ID(OUT)));
inv_in2out[in_bit] = out_bit;
inv_out2in[out_bit] = in_bit;
inv_in2cell[in_bit] = cell;
@ -175,15 +175,15 @@ struct Greenpak4DffInvPass : public Pass {
for (auto cell : dff_cells)
{
SigBit d_bit = sigmap(cell->getPort("\\D"));
SigBit q_bit = sigmap(cell->hasPort("\\Q") ? cell->getPort("\\Q") : cell->getPort("\\nQ"));
SigBit d_bit = sigmap(cell->getPort(ID::D));
SigBit q_bit = sigmap(cell->hasPort(ID::Q) ? cell->getPort(ID::Q) : cell->getPort(ID(nQ)));
while (inv_out2in.count(d_bit))
{
sig_use_cnt[d_bit]--;
invert_gp_dff(cell, true);
d_bit = inv_out2in.at(d_bit);
cell->setPort("\\D", d_bit);
cell->setPort(ID::D, d_bit);
sig_use_cnt[d_bit]++;
}
@ -197,10 +197,10 @@ struct Greenpak4DffInvPass : public Pass {
inv_in2cell.erase(q_bit);
invert_gp_dff(cell, false);
if (cell->hasPort("\\Q"))
cell->setPort("\\Q", new_q_bit);
if (cell->hasPort(ID::Q))
cell->setPort(ID::Q, new_q_bit);
else
cell->setPort("\\nQ", new_q_bit);
cell->setPort(ID(nQ), new_q_bit);
}
}
}

14
techlibs/ice40/ice40_braminit.cc
View file

@ -33,15 +33,15 @@ static void run_ice40_braminit(Module *module)
uint16_t mem[256];
/* Only consider cells we're interested in */
if (cell->type != "\\SB_RAM40_4K" &&
cell->type != "\\SB_RAM40_4KNR" &&
cell->type != "\\SB_RAM40_4KNW" &&
cell->type != "\\SB_RAM40_4KNRNW")
if (cell->type != ID(SB_RAM40_4K) &&
cell->type != ID(SB_RAM40_4KNR) &&
cell->type != ID(SB_RAM40_4KNW) &&
cell->type != ID(SB_RAM40_4KNRNW))
continue;
if (!cell->hasParam("\\INIT_FILE"))
if (!cell->hasParam(ID(INIT_FILE)))
continue;
std::string init_file = cell->getParam("\\INIT_FILE").decode_string();
cell->unsetParam("\\INIT_FILE");
std::string init_file = cell->getParam(ID(INIT_FILE)).decode_string();
cell->unsetParam(ID(INIT_FILE));
if (init_file == "")
continue;

30
techlibs/ice40/ice40_ffinit.cc
View file

@ -62,11 +62,11 @@ struct Ice40FfinitPass : public Pass {
for (auto wire : module->selected_wires())
{
if (wire->attributes.count("\\init") == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
Const initval = wire->attributes.at("\\init");
Const initval = wire->attributes.at(ID::init);
init_wires.insert(wire);
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
@ -93,9 +93,9 @@ struct Ice40FfinitPass : public Pass {
}
pool<IdString> sb_dff_types = {
"\\SB_DFF", "\\SB_DFFE", "\\SB_DFFSR", "\\SB_DFFR", "\\SB_DFFSS", "\\SB_DFFS", "\\SB_DFFESR",
"\\SB_DFFER", "\\SB_DFFESS", "\\SB_DFFES", "\\SB_DFFN", "\\SB_DFFNE", "\\SB_DFFNSR", "\\SB_DFFNR",
"\\SB_DFFNSS", "\\SB_DFFNS", "\\SB_DFFNESR", "\\SB_DFFNER", "\\SB_DFFNESS", "\\SB_DFFNES"
ID(SB_DFF), ID(SB_DFFE), ID(SB_DFFSR), ID(SB_DFFR), ID(SB_DFFSS), ID(SB_DFFS), ID(SB_DFFESR),
ID(SB_DFFER), ID(SB_DFFESS), ID(SB_DFFES), ID(SB_DFFN), ID(SB_DFFNE), ID(SB_DFFNSR), ID(SB_DFFNR),
ID(SB_DFFNSS), ID(SB_DFFNS), ID(SB_DFFNESR), ID(SB_DFFNER), ID(SB_DFFNESS), ID(SB_DFFNES)
};
for (auto cell : module->selected_cells())
@ -103,8 +103,8 @@ struct Ice40FfinitPass : public Pass {
if (!sb_dff_types.count(cell->type))
continue;
SigSpec sig_d = cell->getPort("\\D");
SigSpec sig_q = cell->getPort("\\Q");
SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort(ID::Q);
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
@ -133,14 +133,14 @@ struct Ice40FfinitPass : public Pass {
if (type_str.back() == 'S') {
type_str.back() = 'R';
cell->type = type_str;
cell->setPort("\\R", cell->getPort(ID::S));
cell->setPort(ID::R, cell->getPort(ID::S));
cell->unsetPort(ID::S);
} else
if (type_str.back() == 'R') {
type_str.back() = 'S';
cell->type = type_str;
cell->setPort(ID::S, cell->getPort("\\R"));
cell->unsetPort("\\R");
cell->setPort(ID::S, cell->getPort(ID::R));
cell->unsetPort(ID::R);
}
Wire *new_bit_d = module->addWire(NEW_ID);
@ -149,17 +149,17 @@ struct Ice40FfinitPass : public Pass {
module->addNotGate(NEW_ID, bit_d, new_bit_d);
module->addNotGate(NEW_ID, new_bit_q, bit_q);
cell->setPort("\\D", new_bit_d);
cell->setPort("\\Q", new_bit_q);
cell->setPort(ID::D, new_bit_d);
cell->setPort(ID::Q, new_bit_q);
}
for (auto wire : init_wires)
{
if (wire->attributes.count("\\init") == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
Const &initval = wire->attributes.at("\\init");
Const &initval = wire->attributes.at(ID::init);
bool remove_attribute = true;
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
@ -170,7 +170,7 @@ struct Ice40FfinitPass : public Pass {
}
if (remove_attribute)
wire->attributes.erase("\\init");
wire->attributes.erase(ID::init);
}
}
}

20
techlibs/ice40/ice40_ffssr.cc
View file

@ -49,10 +49,10 @@ struct Ice40FfssrPass : public Pass {
extra_args(args, argidx, design);
pool<IdString> sb_dff_types;
sb_dff_types.insert("\\SB_DFF");
sb_dff_types.insert("\\SB_DFFE");
sb_dff_types.insert("\\SB_DFFN");
sb_dff_types.insert("\\SB_DFFNE");
sb_dff_types.insert(ID(SB_DFF));
sb_dff_types.insert(ID(SB_DFFE));
sb_dff_types.insert(ID(SB_DFFN));
sb_dff_types.insert(ID(SB_DFFNE));
for (auto module : design->selected_modules())
{
@ -69,7 +69,7 @@ struct Ice40FfssrPass : public Pass {
continue;
}
if (cell->type != "$_MUX_")
if (cell->type != ID($_MUX_))
continue;
SigBit bit_a = sigmap(cell->getPort(ID::A));
@ -81,10 +81,10 @@ struct Ice40FfssrPass : public Pass {
for (auto cell : ff_cells)
{
if (cell->get_bool_attribute("\\dont_touch"))
if (cell->get_bool_attribute(ID(dont_touch)))
continue;
SigSpec sig_d = cell->getPort("\\D");
SigSpec sig_d = cell->getPort(ID::D);
if (GetSize(sig_d) < 1)
continue;
@ -117,11 +117,11 @@ struct Ice40FfssrPass : public Pass {
if (sr_val == State::S1) {
cell->type = cell->type.str() + "SS";
cell->setPort(ID::S, sr_sig);
cell->setPort("\\D", bit_d);
cell->setPort(ID::D, bit_d);
} else {
cell->type = cell->type.str() + "SR";
cell->setPort("\\R", sr_sig);
cell->setPort("\\D", bit_d);
cell->setPort(ID::R, sr_sig);
cell->setPort(ID::D, bit_d);
}
}
}

86
techlibs/ice40/ice40_opt.cc
View file

@ -41,26 +41,26 @@ static void run_ice40_opts(Module *module)
for (auto cell : module->selected_cells())
{
if (!cell->type.in("\\SB_LUT4", "\\SB_CARRY", "$__ICE40_CARRY_WRAPPER"))
if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), ID($__ICE40_CARRY_WRAPPER)))
continue;
if (cell->has_keep_attr())
continue;
if (cell->type == "\\SB_LUT4")
if (cell->type == ID(SB_LUT4))
{
sb_lut_cells.push_back(cell);
continue;
}
if (cell->type == "\\SB_CARRY")
if (cell->type == ID(SB_CARRY))
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
get_bit_or_zero(cell->getPort("\\I0")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\CI"))
get_bit_or_zero(cell->getPort(ID(I0))),
get_bit_or_zero(cell->getPort(ID(I1))),
get_bit_or_zero(cell->getPort(ID::CI))
};
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
@ -79,8 +79,8 @@ static void run_ice40_opts(Module *module)
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output);
optimized_co.insert(sigmap(cell->getPort(ID::CO)[0]));
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
@ -89,7 +89,7 @@ static void run_ice40_opts(Module *module)
continue;
}
if (cell->type == "$__ICE40_CARRY_WRAPPER")
if (cell->type == ID($__ICE40_CARRY_WRAPPER))
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
@ -97,7 +97,7 @@ static void run_ice40_opts(Module *module)
SigBit inbit[3] = {
cell->getPort(ID::A),
cell->getPort(ID::B),
cell->getPort("\\CI")
cell->getPort(ID::CI)
};
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
@ -116,7 +116,7 @@ static void run_ice40_opts(Module *module)
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
optimized_co.insert(sigmap(cell->getPort(ID::CO)[0]));
auto it = cell->attributes.find(ID(SB_LUT4.name));
if (it != cell->attributes.end()) {
module->rename(cell, it->second.decode_string());
@ -124,9 +124,9 @@ static void run_ice40_opts(Module *module)
for (const auto &a : cell->attributes)
if (a.first.begins_with("\\SB_LUT4.\\"))
new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
else if (a.first == ID(src))
else if (a.first == ID::src)
new_attr.insert(std::make_pair(a.first, a.second));
else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived)))
else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
continue;
else if (a.first.begins_with("\\SB_CARRY.\\"))
continue;
@ -134,22 +134,22 @@ static void run_ice40_opts(Module *module)
log_abort();
cell->attributes = std::move(new_attr);
}
module->connect(cell->getPort("\\CO")[0], replacement_output);
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
cell->setPort(ID::Y, cell->getPort("\\O"));
cell->type = ID($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
cell->setPort(ID::Y, cell->getPort(ID::O));
cell->unsetPort(ID::B);
cell->unsetPort("\\CI");
cell->unsetPort("\\I0");
cell->unsetPort("\\I3");
cell->unsetPort("\\CO");
cell->unsetPort("\\O");
cell->setParam("\\WIDTH", 4);
cell->unsetParam("\\I3_IS_CI");
cell->unsetPort(ID::CI);
cell->unsetPort(ID(I0));
cell->unsetPort(ID(I3));
cell->unsetPort(ID::CO);
cell->unsetPort(ID::O);
cell->setParam(ID::WIDTH, 4);
cell->unsetParam(ID(I3_IS_CI));
}
continue;
}
@ -159,10 +159,10 @@ static void run_ice40_opts(Module *module)
{
SigSpec inbits;
inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
inbits.append(get_bit_or_zero(cell->getPort(ID(I0))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I1))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I2))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I3))));
sigmap.apply(inbits);
if (optimized_co.count(inbits[0])) goto remap_lut;
@ -177,23 +177,23 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
cell->type ="$lut";
cell->setParam("\\WIDTH", 4);
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT");
cell->type = ID($lut);
cell->setParam(ID::WIDTH, 4);
cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT)));
cell->unsetParam(ID(LUT_INIT));
cell->setPort(ID::A, SigSpec({
get_bit_or_zero(cell->getPort("\\I3")),
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\I0"))
get_bit_or_zero(cell->getPort(ID(I3))),
get_bit_or_zero(cell->getPort(ID(I2))),
get_bit_or_zero(cell->getPort(ID(I1))),
get_bit_or_zero(cell->getPort(ID(I0)))
}));
cell->setPort(ID::Y, cell->getPort("\\O")[0]);
cell->unsetPort("\\I0");
cell->unsetPort("\\I1");
cell->unsetPort("\\I2");
cell->unsetPort("\\I3");
cell->unsetPort("\\O");
cell->setPort(ID::Y, cell->getPort(ID::O)[0]);
cell->unsetPort(ID(I0));
cell->unsetPort(ID(I1));
cell->unsetPort(ID(I2));
cell->unsetPort(ID(I3));
cell->unsetPort(ID::O);
cell->check();
simplemap_lut(module, cell);

32
techlibs/sf2/sf2_iobs.cc
View file

@ -34,14 +34,14 @@ static void handle_iobufs(Module *module, bool clkbuf_mode)
for (auto cell : module->cells())
{
if (clkbuf_mode && cell->type == "\\SLE") {
for (auto bit : sigmap(cell->getPort("\\CLK")))
if (clkbuf_mode && cell->type == ID(SLE)) {
for (auto bit : sigmap(cell->getPort(ID::CLK)))
clk_bits.insert(bit);
}
if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUFF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
"\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUFF_DIFF", "\\CLKBUF_DIFF",
"\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF")) {
for (auto bit : sigmap(cell->getPort("\\PAD")))
if (cell->type.in(ID(INBUF), ID(OUTBUF), ID(TRIBUFF), ID(BIBUF), ID(CLKBUF), ID(CLKBIBUF),
ID(INBUF_DIFF), ID(OUTBUF_DIFF), ID(BIBUFF_DIFF), ID(TRIBUFF_DIFF), ID(CLKBUF_DIFF),
ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF))) {
for (auto bit : sigmap(cell->getPort(ID(PAD))))
handled_io_bits.insert(bit);
}
}
@ -65,13 +65,13 @@ static void handle_iobufs(Module *module, bool clkbuf_mode)
IdString buf_type, buf_port;
if (wire->port_output) {
buf_type = "\\OUTBUF";
buf_port = "\\D";
buf_type = ID(OUTBUF);
buf_port = ID::D;
} else if (clkbuf_mode && clk_bits.count(canonical_bit)) {
buf_type = "\\CLKBUF";
buf_type = ID(CLKBUF);
buf_port = ID::Y;
} else {
buf_type = "\\INBUF";
buf_type = ID(INBUF);
buf_port = ID::Y;
}
@ -96,7 +96,7 @@ static void handle_iobufs(Module *module, bool clkbuf_mode)
module->rewrite_sigspecs(rewrite_function);
for (auto &it : pad_bits)
it.first->setPort("\\PAD", it.second);
it.first->setPort(ID(PAD), it.second);
}
static void handle_clkint(Module *module)
@ -108,12 +108,12 @@ static void handle_clkint(Module *module)
for (auto cell : module->cells())
{
if (cell->type == "\\SLE") {
for (auto bit : sigmap(cell->getPort("\\CLK")))
if (cell->type == ID(SLE)) {
for (auto bit : sigmap(cell->getPort(ID::CLK)))
clk_bits.insert(bit);
}
if (cell->type.in("\\CLKBUF", "\\CLKBIBUF", "\\CLKBUF_DIFF", "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF",
"\\CLKINT", "\\CLKINT_PRESERVE", "\\GCLKINT", "\\RCLKINT", "\\RGCLKINT")) {
if (cell->type.in(ID(CLKBUF), ID(CLKBIBUF), ID(CLKBUF_DIFF), ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF),
ID(CLKINT), ID(CLKINT_PRESERVE), ID(GCLKINT), ID(RCLKINT), ID(RGCLKINT))) {
for (auto bit : sigmap(cell->getPort(ID::Y)))
handled_clk_bits.push_back(bit);
}
@ -134,7 +134,7 @@ static void handle_clkint(Module *module)
for (auto &bit : sig) {
SigBit canonical_bit = sigmap(bit);
if (clk_bits.count(canonical_bit)) {
Cell *c = module->addCell(NEW_ID, "\\CLKINT");
Cell *c = module->addCell(NEW_ID, ID(CLKINT));
SigBit new_bit = module->addWire(NEW_ID);
c->setPort(ID::A, new_bit);
c->setPort(ID::Y, bit);

26
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -146,12 +146,12 @@ struct XilinxDffOptPass : public Pass {
if (cell->get_bool_attribute(ID::keep))
continue;
if (cell->type == ID(INV)) {
SigBit sigout = sigmap(cell->getPort(ID(O)));
SigBit sigin = sigmap(cell->getPort(ID(I)));
SigBit sigout = sigmap(cell->getPort(ID::O));
SigBit sigin = sigmap(cell->getPort(ID::I));
bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell);
} else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) {
SigBit sigout = sigmap(cell->getPort(ID(O)));
const Const &init = cell->getParam(ID(INIT));
SigBit sigout = sigmap(cell->getPort(ID::O));
const Const &init = cell->getParam(ID::INIT);
std::vector<SigBit> sigin;
sigin.push_back(sigmap(cell->getPort(ID(I0))));
if (cell->type == ID(LUT1))
@ -199,7 +199,7 @@ lut_sigin_done:
continue;
// Don't bother if D has more than one use.
SigBit sig_D = sigmap(cell->getPort(ID(D)));
SigBit sig_D = sigmap(cell->getPort(ID::D));
if (bit_uses[sig_D] > 2)
continue;
@ -223,7 +223,7 @@ lut_sigin_done:
bool worthy_post_r = false;
// First, unmap CE.
SigBit sig_Q = sigmap(cell->getPort(ID(Q)));
SigBit sig_Q = sigmap(cell->getPort(ID::Q));
SigBit sig_CE = sigmap(cell->getPort(ID(CE)));
LutData lut_ce = LutData(Const(2, 2), {sig_CE});
auto it_CE = bit_to_lut.find(sig_CE);
@ -247,7 +247,7 @@ lut_sigin_done:
// Second, unmap S, if any.
lut_d_post_s = lut_d_post_ce;
if (has_s) {
SigBit sig_S = sigmap(cell->getPort(ID(S)));
SigBit sig_S = sigmap(cell->getPort(ID::S));
LutData lut_s = LutData(Const(2, 2), {sig_S});
bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool();
auto it_S = bit_to_lut.find(sig_S);
@ -269,7 +269,7 @@ lut_sigin_done:
// Third, unmap R, if any.
lut_d_post_r = lut_d_post_s;
if (has_r) {
SigBit sig_R = sigmap(cell->getPort(ID(R)));
SigBit sig_R = sigmap(cell->getPort(ID::R));
LutData lut_r = LutData(Const(2, 2), {sig_R});
bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool();
auto it_R = bit_to_lut.find(sig_R);
@ -307,11 +307,11 @@ unmap:
// Okay, we're doing it. Unmap ports.
if (worthy_post_r) {
cell->unsetParam(ID(IS_R_INVERTED));
cell->setPort(ID(R), Const(0, 1));
cell->setPort(ID::R, Const(0, 1));
}
if (has_s && (worthy_post_r || worthy_post_s)) {
cell->unsetParam(ID(IS_S_INVERTED));
cell->setPort(ID(S), Const(0, 1));
cell->setPort(ID::S, Const(0, 1));
}
cell->setPort(ID(CE), Const(1, 1));
cell->unsetParam(ID(IS_D_INVERTED));
@ -342,9 +342,9 @@ unmap:
}
lut_cell->attributes = cell_d->attributes;
Wire *lut_out = module->addWire(NEW_ID);
lut_cell->setParam(ID(INIT), final_lut.first);
cell->setPort(ID(D), lut_out);
lut_cell->setPort(ID(O), lut_out);
lut_cell->setParam(ID::INIT, final_lut.first);
cell->setPort(ID::D, lut_out);
lut_cell->setPort(ID::O, lut_out);
lut_cell->setPort(ID(I0), final_lut.second[0]);
if (GetSize(final_lut.second) >= 2)
lut_cell->setPort(ID(I1), final_lut.second[1]);