457 commits

Author	SHA1	Message	Date
Eddie Hung	5c68da4150	Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf	2019-10-05 09:27:12 -07:00
Clifford Wolf	10d0bad67e	Update README.md	2019-10-05 18:13:04 +02:00
Eddie Hung	f90a4b1e24	Missed this	2019-10-05 08:57:37 -07:00
Eddie Hung	991c2ca95b	Add comment on why we have to match for clock-enable/reset muxes	2019-10-05 08:56:37 -07:00
Eddie Hung	ebb059896a	Add note on pattern detector	2019-10-05 08:53:01 -07:00
Miodrag Milanović	7c074ef844	Merge pull request #1436 from YosysHQ/mmicko/msvc_fix ... Fixes for MSVC build	2019-10-05 07:48:30 +02:00
Eddie Hung	792cd31052	Add comments for xilinx_dsp_cascade	2019-10-04 22:31:04 -07:00
Eddie Hung	12fd2ec4f0	Improve comments for xilinx_dsp_CREG	2019-10-04 22:31:04 -07:00
Eddie Hung	14e4aeece6	Fix comment	2019-10-04 22:31:04 -07:00
Eddie Hung	8027ebf05b	Restore optimisation for sigM.empty()	2019-10-04 22:31:04 -07:00
Eddie Hung	77d7a5c14a	Retry on fixing TODOs	2019-10-04 22:31:04 -07:00
Eddie Hung	52583ecff8	Revert "Fix TODOs" ... This reverts commit 8674a6c68d563908014d16671567459499c6dc99.	2019-10-04 22:31:04 -07:00
Eddie Hung	6d68972619	More comments, cleanup	2019-10-04 22:31:04 -07:00
Eddie Hung	7de9c33931	Fix TODOs	2019-10-04 22:31:04 -07:00
Eddie Hung	983068103e	Consistency	2019-10-04 22:31:04 -07:00
Eddie Hung	cf82b38478	Add comments for xilinx_dsp	2019-10-04 22:31:04 -07:00
Eddie Hung	74ef8feeaf	Fix xilinx_dsp for unsigned extensions	2019-10-04 16:46:15 -07:00
Miodrag Milanovic	c0b14cfea7	Fixes for MSVC build	2019-10-04 16:29:46 +02:00
Eddie Hung	e9645c7fa7	Fix broken CI, check reset even for constants, trim rstmux	2019-10-02 21:26:26 -07:00
Eddie Hung	d99810ad8a	Refactor peepopt_dffmux and be sensitive to \init when trimming	2019-10-02 18:01:45 -07:00
Eddie Hung	aebbfffd71	Ooops AREG and BREG to default to -1	2019-09-27 11:57:53 -07:00
Eddie Hung	26657037b8	Update doc with max cascade chain of 20	2019-09-26 14:31:02 -07:00
Eddie Hung	5b9deef10d	Do not always zero out C (e.g. during cascade breaks)	2019-09-26 13:59:05 -07:00
Eddie Hung	95f0dd57df	Update doc	2019-09-26 13:44:41 -07:00
Eddie Hung	58f31096ab	Zero out ports	2019-09-26 13:40:38 -07:00
Eddie Hung	af59856ba1	xilinx_dsp_cascade to also cascade AREG and BREG	2019-09-26 13:29:18 -07:00
Eddie Hung	832216dab0	Try recursive pmgen for P cascade	2019-09-26 12:09:57 -07:00
Eddie Hung	bd8661e024	CREG to check for \keep	2019-09-26 10:32:01 -07:00
Eddie Hung	c0bb1d22e8	Remove newline	2019-09-26 10:31:55 -07:00
Eddie Hung	f1de93edf5	Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)	2019-09-25 22:58:03 -07:00
Eddie Hung	cd8a640989	Reject if (* init *) present	2019-09-25 18:21:08 -07:00
Eddie Hung	aeb1539818	Rework xilinx_dsp postAdd for new wreduce call	2019-09-25 17:22:30 -07:00
Eddie Hung	5f8917c984	Fix memory issue since SigSpec& could be invalidated	2019-09-25 16:45:51 -07:00
Eddie Hung	486dd7c483	unextend only used in init	2019-09-25 14:05:59 -07:00
Eddie Hung	53ea5daa42	Call 'wreduce' after mul2dsp to avoid unextend()	2019-09-25 14:04:36 -07:00
Eddie Hung	e556d48d45	Set [AB]CASCREG to legal values	2019-09-23 16:00:11 -07:00
Eddie Hung	b824a56cde	Comment to explain separating CREG packing	2019-09-23 13:58:10 -07:00
Eddie Hung	15dfbc8125	Separate out CREG packing into new pattern, to avoid conflict with PREG	2019-09-23 13:27:10 -07:00
Eddie Hung	26a6c55665	Move log_debug("\n") later	2019-09-23 13:27:00 -07:00
Eddie Hung	d0dbbc2605	Move unextend initialisation later	2019-09-23 13:26:34 -07:00
Eddie Hung	a67af3d5e5	Use new port() overload once more	2019-09-23 13:00:44 -07:00
Eddie Hung	53817b8575	Use new port/param overload in pmg	2019-09-20 14:21:22 -07:00
Eddie Hung	d122083a11	Output pattern matcher items as log_debug()	2019-09-20 12:42:28 -07:00
Eddie Hung	95644b00cb	OPMODE is port not param	2019-09-20 12:37:29 -07:00
Eddie Hung	eb597431f0	Do not run xilinx_dsp_cascadeAB for now	2019-09-20 12:18:37 -07:00
Eddie Hung	0bca366bcd	WIP for xiinx_dsp_cascadeAB	2019-09-20 12:07:14 -07:00
Eddie Hung	b0ad2592be	Run until convergence	2019-09-20 12:04:16 -07:00
Eddie Hung	1b892ca1be	Cleanup ice40_dsp.pmg	2019-09-20 12:03:45 -07:00
Eddie Hung	d88903e610	Cleanup xilinx_dsp	2019-09-20 12:03:25 -07:00
Eddie Hung	1809f463fb	More exceptions	2019-09-20 12:03:10 -07:00