548 commits

Author	SHA1	Message	Date
Akash Levy	76c12f8f8c	Merge branch 'YosysHQ:main' into main	2025-11-03 13:38:04 -05:00
Mohamed Gaber	dec28f65ae	Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11	2025-10-26 02:39:43 +03:00
Robert O'Callahan	25aafab86b	Set port_id for Verific PortBus wires	2025-10-23 20:51:53 +00:00
Miodrag Milanovic	1f11b2c529	verific: Add src to message missed in #5406	2025-10-13 15:16:17 +02:00
Miodrag Milanovic	dc959cdf4a	verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS	2025-10-13 15:16:17 +02:00
Miodrag Milanovic	9570b39519	verifix: fix bits() deprecation warnings	2025-10-13 09:57:22 +02:00
Miodrag Milanovic	2f8f421dee	verifix: fix bits() deprecation warnings	2025-10-13 09:47:18 +02:00
Akash Levy	54653fc82c	Reenable Verific opt and comment out clock enable muxing	2025-10-12 07:52:32 -07:00
Akash Levy	6993fc2540	Flush during import	2025-10-12 07:52:12 -07:00
N. Engelhardt	0b6adf832b	verific: print source location of problematic object on import error (if available)	2025-10-03 12:57:49 +02:00
Akash Levy	623c54d513	Only do SFCU if has VHDL	2025-10-02 06:02:39 -07:00
Akash Levy	16215b8786	Merge upstream	2025-09-29 20:58:56 -07:00
Akash Levy	507d43a9b8	Fixups	2025-09-28 06:16:07 -07:00
Jannis Harder	83dd99efb7	verific: New -sva-continue-on-error import option ... This option allows you to process a design that includes unsupported SVA. Unsupported SVA gets imported as formal cells using 'x inputs and with the `unsupported_sva` attribute set. This allows you to get a complete list of defined properties or to check only a supported subset of properties. To ensure no properties are unintentionally skipped for actual verification, even in cases where `-sva-continue-on-error` is used by default to read and inspect a design, `hierarchy -simcheck` and `hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva` property cells remain in the design.	2025-09-24 18:58:54 +02:00
Akash Levy	60d969530b	Bump to latest	2025-09-21 01:10:04 -07:00
Robert O'Callahan	a7c46f7b4a	Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()	2025-09-16 23:02:16 +00:00
Robert O'Callahan	5ac6858f26	Remove .c_str() from log_cmd_error() and log_file_error() parameters	2025-09-16 22:59:08 +00:00
Robert O'Callahan	1a367b907c	Use fast path for 32-bit Const integer constructor in more places	2025-09-16 03:17:24 +00:00
Akash Levy	f5cb0c328f	Bump Yosys to latest	2025-09-13 04:35:52 -07:00
Robert O'Callahan	e0ae7b7af4	Remove .c_str() calls from log()/log_error() ... There are some leftovers, but this is an easy regex-based approach that removes most of them.	2025-09-11 20:59:37 +00:00
Akash Levy	1b3375d8df	Merge upstream in	2025-09-09 05:50:48 -07:00
Robert O'Callahan	c7df6954b9	Remove .c_str() from stringf parameters	2025-09-01 23:34:42 +00:00
Akash Levy	3311056d81	Revert "Revert some vhdl stuff" ... This reverts commit 6a9102346a.	2025-08-08 01:16:49 -07:00
Akash Levy	6a9102346a	Revert some vhdl stuff	2025-08-08 01:05:57 -07:00
Akash Levy	0e50fd3b74	Restricted multiport	2025-08-08 00:37:20 -07:00
Akash Levy	cc733fd11b	Merge from upstream	2025-07-30 22:50:14 -07:00
Miodrag Milanovic	f92a53ec31	verific: handle nullptr for message_id	2025-07-30 10:51:54 +02:00
Mike Inouye	0314db80ea	Correctly reset Verific flags to Yosys defaults after -import and warn this has occurred. ... Co-authored-by: Chris Pearce <chris@pearce.org.nz> Signed-off-by: Mike Inouye <mikeinouye@google.com>	2025-07-25 19:15:01 +00:00
Akash Levy	082adf8684	Merge branch 'YosysHQ:main' into main	2025-07-15 00:04:28 -04:00
N. Engelhardt	e47f5369fd	verificsva: check -L value is small enough for code to work	2025-07-09 15:58:35 +02:00
Akash Levy	fbc8aa46d4	Merge branch 'YosysHQ:main' into main	2025-07-04 13:37:04 -04:00
Miodrag Milanovic	eed3bc243f	verific: enable replacing const exprs in static elaboration by default	2025-07-02 11:54:19 +02:00
Akash Levy	64d99416c1	Do not downgrade any warnings	2025-06-09 15:11:00 -07:00
Akash Levy	447a73ea86	Merge branch 'YosysHQ:main' into main	2025-06-09 14:51:56 -07:00
N. Engelhardt	f22248f056	downgrade verific warnings about common coding styles	2025-06-06 16:30:50 +02:00
Akash Levy	e50a5974f7	Get rid of SYNTHESIS redefinition warning	2025-05-28 08:33:56 +02:00
Akash Levy	3a23e772dd	Merge branch 'YosysHQ:main' into main	2025-05-24 12:11:52 -07:00
Emil J. Tywoniak	e5171d6aa1	verific: support single_bit_vector	2025-05-12 13:23:29 +02:00
Akash Levy	3bcbfe4dde	verific -set_relaxed_file_libext_modes	2025-05-08 23:43:23 -07:00
Akash Levy	f3d24aea76	Add spaces in verific	2025-05-08 22:24:10 -07:00
Akash Levy	380850321d	Refactor verific -optimization and -no_split_complex_ports into verific pass	2025-05-08 15:59:47 -07:00
Akash Levy	618cf9d372	Merge branch 'YosysHQ:main' into main	2025-04-28 13:57:29 -07:00
Miodrag Milanovic	22e6ce4282	verific: bit blast RAM if using mem2reg attribute	2025-04-14 15:24:11 +02:00
Akash Levy	61715c2c28	Fix memory too large issue	2025-04-04 03:22:22 -07:00
Akash Levy	f218b5ba58	Revert "Represent memory size with size_t" ... This reverts commit bb5f8415af.	2025-04-04 03:20:07 -07:00
Akash Levy	bb5f8415af	Represent memory size with size_t	2025-04-04 02:04:34 -07:00
Akash Levy	4bd08ac362	Merge branch 'YosysHQ:main' into main	2025-04-01 22:10:43 -07:00
Miodrag Milanovic	72f2185a94	verific: fix restoring msg state after blackbox import	2025-04-01 17:35:59 +02:00
Akash Levy	d2028feefe	Set Verific flags via -cfg instead of in Yosys	2025-03-25 22:41:06 -07:00
Akash Levy	95f489beec	Merge nice gzip refactor	2025-03-20 16:47:12 -07:00