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17512 commits 143 branches 70 tags 52 MiB
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Author SHA1 Message Date
Emil J. Tywoniak
b408a059ad rtlil: add dump_sigmap for hacky signorm debugging 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
8457802dda techmap: disable signorm more 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
80f2c38a3e techmap: disable signorm 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
8393a7d241 opt_hier: disable signorm 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
9521b22907 timinginfo: disable output wire check due to signorm 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
a7b62c6bc3 rtlil: forbid rewrite_sigspecs in signorm 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
055705aebc opt_merge_inc: re add initvals deletion 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
8a014a1f2d synth_ice40: always read abc9 model to understand port direction 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
04311dd529 tests: adjust to input_port and init behavior (sketchy) 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
ae78170db8 tests: adjust to input_port and init behavior (sketchy) 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
df0da642d2 tests: adjust to input_port and init behavior (sketchy) 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
8d02d94b50 wreduce: fixup initvals after setPort 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
d50f9b7bb1 ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
3031dd79d9 tests: adjust to input_port and init behavior (sketchy) 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
3b956cea1b rtlil: fix zero width SigSpec crash in signorm setPort unsetPort 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
328ffd79d0 bug2920: disable 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
479ab70890 rtlil_bufnorm: fix cell deletion deferral bug 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
f50f03d972 tests: adjust to input_port and init behavior (sketchy) 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
65dd0d59a5 check: don't fail on $input_port 2026-07-17 23:32:34 +02:00
Emil J. Tywoniak
d93ab0d07f mem: fix signorm cell type morph 2026-07-17 23:32:34 +02:00
Jannis Harder
b84beb598f WIP half broken snapshot 2026-07-17 23:32:20 +02:00
Jannis Harder
51fc03688a WIP remove dead code 2026-07-17 23:31:11 +02:00
Miodrag Milanović
22c15a7ecd
Merge pull request #6034 from YosysHQ/mmicko/system_libs 
cmake: Use system libs when available
 2026-07-13 15:50:10 +00:00
Miodrag Milanovic
3541e31457 Add option to use bundled libs 2026-07-13 16:50:06 +02:00
Miodrag Milanovic
30ba4328e7 Use system libs when available 2026-07-13 15:26:00 +02:00
nella
dddf137888
Merge pull request #6024 from YosysHQ/nella/scl-build-date 
Include build datetime in scl cache hash
 2026-07-13 11:54:45 +00:00
Miodrag Milanović
0e82bbefe5
Merge pull request #6027 from YosysHQ/mmicko/skip_fix 
codecov: fix not skipping when pushing on
 2026-07-10 16:12:03 +00:00
Miodrag Milanovic
0f8f70eb84 codecov: fix not skipping when pushing on 2026-07-10 17:55:11 +02:00
Miodrag Milanović
6fdd5bb11e
Merge pull request #6026 from YosysHQ/mmicko/coverage_main 
codecov: Upload coverage on main
 2026-07-10 15:25:25 +00:00
Miodrag Milanovic
16766b26e9 codecov: Upload coverage on main 2026-07-10 17:09:20 +02:00
nella
ede98b81ac
Merge pull request #6023 from b-michi/michaelbaier/sc-649/segmentation-fault-during-proc-init-with 
Michaelbaier/sc 649/segmentation fault during proc init with
 2026-07-10 13:07:58 +00:00
nella
eb93f5a066 Add scl caching test. 2026-07-10 14:52:06 +02:00
nella
68aaa34975 Reformat scl cache. 2026-07-10 14:51:58 +02:00
Michael Baier
dca9234d86 Testcases for new truncation checks 2026-07-10 14:37:19 +02:00
Michael Baier
8f0028652a long long to int truncation checks 2026-07-10 14:36:39 +02:00
Miodrag Milanović
be51f7a92c
Merge pull request #6025 from YosysHQ/mmicko/disable_comment 
codecov: Disable PR comments for now
 2026-07-10 11:48:27 +00:00
Miodrag Milanovic
10fcf7a593 codecov: Disable PR comments for now 2026-07-10 13:33:59 +02:00
nella
b678c238e4 Include build datetime in scl cache hash. 2026-07-10 12:44:34 +02:00
Miodrag Milanović
11c30749a4
Merge pull request #6000 from YosysHQ/codecov 
Add initial codecov support
 2026-07-10 10:42:54 +00:00
Miodrag Milanovic
76378e6eb9 Do not add comments in PR 2026-07-10 12:26:47 +02:00
Miodrag Milanovic
f2f3f31646 Add initial codecov support 2026-07-10 12:19:59 +02:00
Michael Baier
1dbefdbd49 Modified pyosys generator.py to support constexpr 2026-07-09 16:32:01 +02:00
Michael Baier
58fc67ee66 Adding Width check to resize 2026-07-09 14:34:56 +02:00
Michael Baier
086c50763d Tescases for Width Limit, Resize and Overflow 2026-07-09 14:34:56 +02:00
Michael Baier
eb4e29810e Fixed Overflow error in checking width 2026-07-09 14:34:56 +02:00
Michael Baier
5cd9efefe3 Adding widht checks to backend 2026-07-09 14:34:56 +02:00
Michael Baier
42092cbc77 Adding width checks to frontend 2026-07-09 14:34:56 +02:00
Michael Baier
ea41b196da Adding Widht Limit 2026-07-09 14:34:56 +02:00
Michael Baier
3adb423e9e Added Testcase for bug1206 2026-07-09 14:34:56 +02:00
Miodrag Milanović
b88b73a99a
Merge pull request #6021 from YosysHQ/release/v0.67 
Release version 0.67
 2026-07-09 10:29:57 +00:00