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Adding widht checks to backend

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This commit is contained in:
Michael Baier 2026-07-09 10:41:42 +02:00
parent 42092cbc77
commit 5cd9efefe3
1 changed files with 3 additions and 0 deletions
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3
kernel/rtlil.cc
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@ -379,6 +379,7 @@ RTLIL::Const::Const(long long val) // default width 32
RTLIL::Const::Const(long long val, int width)
{
log_assert(width >= 0 && width < RTLIL::WIDTH_LIMIT);
flags = RTLIL::CONST_FLAG_NONE;
if ((width & 7) == 0) {
new ((void*)&str_) std::string();
@ -407,6 +408,7 @@ RTLIL::Const::Const(long long val, int width)
RTLIL::Const::Const(RTLIL::State bit, int width)
{
log_assert(width >= 0 && width < RTLIL::WIDTH_LIMIT);
flags = RTLIL::CONST_FLAG_NONE;
new ((void*)&bits_) bitvectype();
tag = backing_tag::bits;
@ -3170,6 +3172,7 @@ void RTLIL::Module::fixup_ports()
RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
{
log_assert(width >= 0 && width < RTLIL::WIDTH_LIMIT);
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = std::move(name);
wire->width = width;