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5626 commits 122 branches 59 tags 43 MiB
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Author SHA1 Message Date
Eddie Hung
b21d29598a Consistency 2019-06-12 09:40:51 -07:00
Eddie Hung
c7f5091c2f Reduce diff with master 2019-06-12 09:34:41 -07:00
Eddie Hung
f9433cc34b Remove abc_flop{,_d} attributes from ice40/cells_sim.v 2019-06-12 09:29:30 -07:00
Eddie Hung
99267f660f Fix spacing 2019-06-12 09:21:52 -07:00
Eddie Hung
738fdfe8f5 Remove wide mux inference 2019-06-12 09:20:46 -07:00
Eddie Hung
b2c72f74f0 Merge branch 'xc7mux' into xaig 2019-06-12 09:14:27 -07:00
Eddie Hung
7eec64a38f Merge branch 'xc7mux' of github.com:YosysHQ/yosys into xc7mux 2019-06-12 09:14:12 -07:00
Eddie Hung
afd620fd5f Typo: wire delay is -W argument 2019-06-12 09:13:53 -07:00
Eddie Hung
2cbcd6224c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit a138381ac3, reversing
changes made to b77c5da769.
 2019-06-12 09:05:02 -07:00
Eddie Hung
882a83c383 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" 
This reverts commit eaee250a6e, reversing
changes made to 935df3569b.
 2019-06-12 09:04:31 -07:00
Eddie Hung
86efe9a616 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" 
This reverts commit 2223ca91b0, reversing
changes made to eaee250a6e.
 2019-06-12 09:01:15 -07:00
Eddie Hung
513c962a71 Merge remote-tracking branch 'origin/xc7mux' into xaig 2019-06-12 08:52:46 -07:00
Eddie Hung
f7a9769c14 Merge remote-tracking branch 'origin/master' into xaig 2019-06-12 08:50:39 -07:00
Eddie Hung
1e838a8913 Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" 2019-06-12 08:49:15 -07:00
Eddie Hung
4c9fde87d1 Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" 
This reverts commit 2dffa4685b.
 2019-06-12 08:48:45 -07:00
Eddie Hung
2dffa4685b Add "-W' wire delay arg to abc9, use from synth_xilinx 2019-06-11 17:10:47 -07:00
Eddie Hung
d26646051c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit 5174082208, reversing
changes made to 54379f9872.
 2019-06-11 16:05:27 -07:00
Eddie Hung
5174082208 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-11 15:48:41 -07:00
Eddie Hung
2f427acc9e Try way that doesn't involve creating a new wire 2019-06-11 15:48:20 -07:00
Eddie Hung
54379f9872 Disable dist RAM boxes due to comb loop 2019-06-11 12:02:51 -07:00
Eddie Hung
8a708d1fdb Remove #ifndef ABC 2019-06-11 12:02:31 -07:00
Eddie Hung
a138381ac3 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-10 16:21:43 -07:00
Eddie Hung
f19aa8d989 If d_bit already in sigbit_chain_next, create extra wire 2019-06-10 16:16:40 -07:00
Eddie Hung
c314ca3c51 Add test 2019-06-10 16:16:26 -07:00
Eddie Hung
b77c5da769 Revert "Revert "Move ff_map back after ABC for shregmap"" 
This reverts commit e473e74565.
 2019-06-10 14:37:09 -07:00
Eddie Hung
a1d4ae78a0 Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" 
This reverts commit 94a5f4e609.
 2019-06-10 14:34:43 -07:00
Eddie Hung
7d27e1e431 Revert "shregmap -tech xilinx_dynamic to work -params and -enpol" 
This reverts commit 45d1bdf83a.
 2019-06-10 14:34:16 -07:00
Eddie Hung
3579d68193 Revert "Refactor to ShregmapTechXilinx7Static" 
This reverts commit e1e37db860.
 2019-06-10 14:34:15 -07:00
Eddie Hung
b6a39351f4 Revert "Add -tech xilinx_static" 
This reverts commit dfe9d95579.
 2019-06-10 14:34:14 -07:00
Eddie Hung
e1dbeb3004 Revert "Continue support for ShregmapTechXilinx7Static" 
This reverts commit 72eda94a66.
 2019-06-10 14:34:14 -07:00
Eddie Hung
9d8563178e Revert "shregmap -tech xilinx_static to handle INIT" 
This reverts commit 935df3569b.
 2019-06-10 14:34:12 -07:00
Eddie Hung
352c532bb2 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-10 11:02:54 -07:00
Eddie Hung
a91ea6612a Add some more comments 2019-06-10 10:27:55 -07:00
David Shah
498c21e735
Merge pull request #1082 from corecode/u4k 
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
 2019-06-10 15:12:23 +01:00
Simon Schubert
abf90b0403 ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k 2019-06-10 11:49:08 +02:00
Clifford Wolf
5a5cbf6458
Merge pull request #1078 from YosysHQ/eddie/muxcover_costs 
Allow muxcover costs to be changed
 2019-06-08 11:31:19 +02:00
Eddie Hung
d5f0b73fd9 Update CHANGELOG 2019-06-07 17:00:36 -07:00
Eddie Hung
816b5f5891 Comment out muxpack (currently broken) 2019-06-07 16:58:57 -07:00
Eddie Hung
5a46a0b385 Fine tune aigerparse 2019-06-07 16:57:32 -07:00
Eddie Hung
1e201a9b01 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-07 16:15:19 -07:00
Eddie Hung
2b350401c4 Fix spacing from spaces to tabs 2019-06-07 15:44:57 -07:00
Clifford Wolf
7395a80690
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger 
Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
 2019-06-07 23:13:34 +02:00
Eddie Hung
f48c6920b7 Add read_aiger to CHANGELOG 2019-06-07 13:12:48 -07:00
Eddie Hung
6934f4bdd5 Fix spacing (entire file is wrong anyway, will fix later) 2019-06-07 11:30:36 -07:00
Eddie Hung
d00ae1d6a8 Remove unnecessary std::getline() for ASCII 2019-06-07 11:28:25 -07:00
Eddie Hung
65924fd12f Test *.aag too, by using *.aig as reference 2019-06-07 11:28:05 -07:00
Eddie Hung
a04521c6b7 Fix read_aiger -- create zero driver, fix init width, parse 'b' 2019-06-07 11:07:15 -07:00
Eddie Hung
abc40924ed Use ABC to convert from AIGER to Verilog 2019-06-07 11:06:57 -07:00
Eddie Hung
ebe29b6659 Use ABC to convert AIGER to Verilog, then sat against Yosys 2019-06-07 11:05:36 -07:00
Eddie Hung
1b113a0574 Add symbols to AIGER test inputs for ABC 2019-06-07 11:05:25 -07:00