mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"

Browse source 
This reverts commit a138381ac3, reversing
changes made to b77c5da769.
This commit is contained in:
Eddie Hung 2019-06-12 09:05:02 -07:00
parent 882a83c383
commit 2cbcd6224c
3 changed files with 3 additions and 59 deletions
Download patch file Download diff file Expand all files Collapse all files

9
passes/techmap/shregmap.cc
View file

@ -293,13 +293,10 @@ struct ShregmapWorker
if (opts.init || sigbit_init.count(q_bit) == 0)
{
auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
if (!r.second) {
if (sigbit_chain_next.count(d_bit)) {
sigbit_with_non_chain_users.insert(d_bit);
Wire *wire = module->addWire(NEW_ID);
module->connect(wire, d_bit);
sigbit_chain_next.insert(std::make_pair(wire, cell));
}
} else
sigbit_chain_next[d_bit] = cell;
sigbit_chain_prev[q_bit] = cell;
continue;

22
tests/various/shregmap.v
View file

@ -1,22 +0,0 @@
module shregmap_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[3], shift1[3]};
endmodule
module $__SHREG_DFF_P_(input C, D, output Q);
parameter DEPTH = 1;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[DEPTH-1];
endmodule

31
tests/various/shregmap.ys
View file

@ -1,31 +0,0 @@
read_verilog shregmap.v
design -copy-to model $__SHREG_DFF_P_
hierarchy -top shregmap_test
prep
design -save gold
techmap
shregmap -init
opt
stat
# show -width
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__SHREG_DFF_P_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
design -load gold
stat
design -load gate
stat