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Add read_aiger to CHANGELOG
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@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
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- Added "gate2lut.v" techmap rule
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- Added "rename -src"
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- Added "equiv_opt" pass
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- Added "read_aiger" frontend
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- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
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