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Update CHANGELOG

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Eddie Hung 2019-06-07 17:00:36 -07:00
parent 816b5f5891
commit d5f0b73fd9
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CHANGELOG
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@ -16,12 +16,10 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
<<<<<<< HEAD
- Added "muxpack" pass
=======
- Added "read_aiger" frontend
>>>>>>> origin/master
- Added "muxpack" pass
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
- "synth_xilinx" to now infer wide multiplexers
Yosys 0.7 .. Yosys 0.8