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Code Activity
9993 commits 102 branches 53 tags 48 MiB
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857 commits

Author SHA1 Message Date
David Shah
6769d31ddb xilinx: Add support for UltraScale[+] BRAM mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:37 +01:00
Marcin Kościelnicki
7b350cacd4 xilinx: Support multiplier mapping for all families. 
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
 2019-10-22 18:06:57 +02:00
Clifford Wolf
a3a7bb9bf7
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg 
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
 2019-10-22 17:36:54 +02:00
Sean Cross
82f60ba938 Makefile: don't assume python is called python3 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
N. Engelhardt
3b405d985e Call memory_dff before DSP mapping to reserve registers (fixes #1447) 2019-10-17 21:33:54 +02:00
Marcin Kościelnicki
526fe4cb89 xilinx: Add simulation model for IBUFG. 2019-10-10 13:16:03 +02:00
Eddie Hung
304e5f9ea4 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-08 13:03:06 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 
Rename abc_* names/attributes to more precisely be abc9_*
 2019-10-08 10:53:38 -07:00
Eddie Hung
4f0818275f Cleanup 2019-10-07 15:58:55 -07:00
Eddie Hung
b2e34f932a Rename $currQ to $abc9_currQ 2019-10-07 15:31:43 -07:00
Eddie Hung
bae3d8705d Update comments in abc9_map.v 2019-10-07 12:54:45 -07:00
Eddie Hung
1dc22607c3 Remove -D_ABC9 2019-10-07 12:21:52 -07:00
Eddie Hung
3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung
6c5e1234e1 Add comment on why partial multipliers are 18x18 2019-10-04 22:31:04 -07:00
Eddie Hung
b47bb5c810 Fix typo in check_label() 2019-10-04 21:43:50 -07:00
Eddie Hung
a2ef93f03a abc -> abc9 2019-10-04 17:56:38 -07:00
Eddie Hung
a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung
bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8 Add temporary abc9 -nomfs and use for synth_xilinx -abc9 2019-10-04 17:35:43 -07:00
Eddie Hung
d4212d128b Use read_args for read_verilog 2019-10-04 17:27:05 -07:00
Eddie Hung
9c23811839 Remove DSP48E1 from *_cells_xtra.v 2019-10-04 17:26:42 -07:00
Eddie Hung
7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung
655f1b2ac5 English 2019-10-03 10:11:25 -07:00
Eddie Hung
5299884f04 More fixes 2019-10-01 13:41:08 -07:00
Eddie Hung
03ebe43e3e Escape Verilog identifiers for legality outside of Yosys 2019-10-01 13:05:56 -07:00
Eddie Hung
e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung
5e9ae90cbb Add explanation to abc_map.v 2019-09-30 15:39:24 -07:00
Eddie Hung
8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
Eddie Hung
5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} 2019-09-30 12:52:43 +02:00
Marcin Kościelnicki
4535f2c694 synth_xilinx: Support latches, remove used-up FF init values. 
Fixes #1387.
 2019-09-30 12:52:43 +02:00
Eddie Hung
f6203e6bd6 Missing endmodule 2019-09-29 21:55:53 -07:00
Eddie Hung
1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung
18ebb86edb FDCE_1 does not have IS_CLR_INVERTED 2019-09-29 11:25:34 -07:00
Eddie Hung
f3e150d9a5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 09:21:51 -07:00
Eddie Hung
79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung
c372e7baf9 Fix box name 2019-09-27 18:49:45 -07:00
Eddie Hung
8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Eddie Hung
b3d8a60cbd Re-order 2019-09-27 14:32:07 -07:00
Eddie Hung
143f82def2 Missing an '&' 2019-09-26 11:13:08 -07:00
Eddie Hung
033aefc0f4 Typo 2019-09-26 10:34:14 -07:00
Eddie Hung
781dda6175 select once 2019-09-26 10:15:05 -07:00
Eddie Hung
27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung
53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Eddie Hung
93363c94a2 Oops. Actually use __NAME__ in ABC_DSP48E1 macro 2019-09-25 10:33:16 -07:00
Eddie Hung
b41d2fb4e4 Add (* techmap_autopurge *) to abc_unmap.v too 2019-09-23 22:02:22 -07:00
Eddie Hung
11ac37733d Add techmap_autopurge to outputs in abc_map.v too 2019-09-23 21:56:28 -07:00
Eddie Hung
27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00