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Code Activity
12351 commits 122 branches 59 tags 73 MiB
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1713 commits

Author SHA1 Message Date
Zachary Snow
6127f22788 Module name scope support 2020-08-20 20:15:08 -04:00
Zachary Snow
74abc3bbfd Allow localparams in constant functions 2020-08-20 20:10:24 -04:00
clairexen
87b9ee330d
Merge pull request #2122 from PeterCrozier/struct_array2 
Support 2D bit arrays in structures. Optimise array indexing.
 2020-08-19 17:58:37 +02:00
clairexen
22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s 
Allow %0s $display format specifier
 2020-08-18 17:39:01 +02:00
clairexen
4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish 
Propagate const_fold through generate blocks and branches
 2020-08-18 17:38:07 +02:00
clairexen
a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock 
Fix generate scoping issues
 2020-08-18 17:37:11 +02:00
Claire Wolf
7f767bf2b7 Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-08-18 17:29:49 +02:00
clairexen
5ee9349647
Merge pull request #2281 from zachjs/const-real 
Allow reals as constant function parameters
 2020-08-18 17:22:20 +02:00
Zachary Snow
2ee0b8ebea Propagate const_fold through generate blocks and branches 2020-08-09 17:21:08 -04:00
Zachary Snow
96ec9acf84 Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
Lukasz Dalek
ba08c25133 Fix subarray access condition 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-08-03 16:16:04 +02:00
Lukasz Dalek
83ddc62034 Rewrite multirange arrays sizes [n] as [n-1:0] 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-08-03 14:48:27 +02:00
Zachary Snow
c3e95eb1ab Fix generate scoping issues 
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456
 2020-07-31 20:32:47 -06:00
Miodrag Milanovic
cc02d58194 Clear last error message 2020-07-29 15:28:33 +02:00
clairexen
45e96d5d87
Merge pull request #2301 from zachjs/for-loop-errors 
Clearer for loop error messages
 2020-07-28 14:07:26 +02:00
Zachary Snow
58da181af9 Clearer for loop error messages 2020-07-25 10:37:16 -06:00
Zachary Snow
f69daf4830 Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
Zachary Snow
59c4ad8ed3 Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
Zachary Snow
f285f7b769 Allow reals as constant function parameters 2020-07-19 20:27:09 -06:00
Claire Wolf
51ee0b683f Treat all bison warnings as errors in verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:57:31 +02:00
Claire Wolf
7a79843cc3 Use %precedence in verilog_parser.y 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:54:28 +02:00
Claire Wolf
24540291c7 Fix bison warnings for missing %empty 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:50:59 +02:00
Claire Wolf
1f4e452609 Run bison with -Wall for verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-15 11:49:36 +02:00
clairexen
021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts 
Restore #2203 and #2244 and fix parser conflicts
 2020-07-15 11:49:09 +02:00
Kamil Rakoczy
02c071888b Add missing semicolons 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-15 10:15:13 +02:00
Claire Wolf
f9ed09423e Add AST_EDGE support to AstNode::detect_latch(), fixes #2241 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-10 18:41:13 +02:00
Kamil Rakoczy
d77b3305d8 Fix S/R conflicts 
This commit fixes S/R conflicts introduced by commit 6f9be93.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-10 15:03:53 +02:00
Kamil Rakoczy
0ffaddee5e Fix R/R conflicts 
This commit fixes R/R conflicts introduced by commit 7e83a51.
Parameter logic is already defined as part of `param_range_type` rule.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-10 15:03:01 +02:00
Kamil Rakoczy
de649b9194 Revert "Revert PRs #2203 and #2244." 
This reverts commit 9c120b89ac.
 2020-07-10 09:59:48 +02:00
whitequark
dc35ef05f9 verilog_parser: turn S/R and R/R conflicts into hard errors. 
Fixes #2253.
 2020-07-09 19:36:59 +00:00
whitequark
9c120b89ac Revert PRs #2203 and #2244. 
This reverts commit 7e83a51fc9.
This reverts commit b422f2e4d0.
This reverts commit 7cb56f34b0.
This reverts commit 6f9be939bd.
This reverts commit 76a34dc5f3.
 2020-07-09 19:36:32 +00:00
Lukasz Dalek
7e83a51fc9 Support logic typed parameters 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-07-06 09:18:48 +02:00
clairexen
3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial 
verific: rewrite initial assume/asserts prior to elaboration
 2020-07-02 17:50:22 +02:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar 
Signed and macro grammar update
 2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast 
Support SystemVerilog Static Cast
 2020-07-01 16:40:20 +02:00
clairexen
9d658a1970
Merge pull request #2136 from zachjs/master 
Allow constant function calls in for loops and generate if and case
 2020-06-30 17:38:49 +02:00
Miodrag Milanovic
561890c4e8 Update verific API version check 2020-06-30 12:13:13 +02:00
Zachary Snow
27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Miodrag Milanovic
b822beb1b2 Fix crash in verific frontend 2020-06-26 20:11:01 +02:00
Lukasz Dalek
6f9be939bd Parse macro call attached semicolon as empty expression 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-26 15:38:20 +02:00
Lukasz Dalek
7cb56f34b0 Fix integer signing grammar 
This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:

parameter integer signed i = 0;
parameter integer unsigned i = 0;

Example of incorrect parameters:

parameter signed integer i = 0;
parameter unsigned integer i = 0;

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:35:56 +02:00
whitequark
12c016ebdc
Merge pull request #2188 from antmicro/missing-operators 
Add logic-assignments operators
 2020-06-26 07:30:27 +00:00
whitequark
d6bdc09422
Merge pull request #2189 from antmicro/optional-labels 
Add support for optional labels
 2020-06-26 07:29:24 +00:00
clairexen
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs 
Use (and ignore) the expression provided to log_assert in NDEBUG builds
 2020-06-25 18:21:51 +02:00
Kamil Rakoczy
539087f417 Support missing sub-assign and and-assign operators 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 13:29:06 +02:00
Miodrag Milanovic
4aec50a863 optimization, all items should have same attributes 2020-06-25 09:18:53 +02:00
Lukasz Dalek
a4b4c22c96 Support missing xor-assign operator 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 14:32:12 +02:00
Lukasz Dalek
a8750b496e Support optional labels at the end of package definition 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 11:57:45 +02:00
Lukasz Dalek
3b81a1b809 Support optional labels at the end of module definition 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 11:57:45 +02:00
Kamil Rakoczy
22408f24c7 Add plus-assignment operator 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:54:30 +02:00