nella
006cbc8f72
Merge pull request #5842 from YosysHQ/nella/opt_dff_elim_improvements
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opt_dff: Eliminate equivalent bits
2026-07-06 12:02:50 +00:00
nella
0e56ca02ed
Make opt_dff -sat conflict with -keepdc.
2026-07-06 13:47:10 +02:00
Miodrag Milanovic
fd3ec58055
Remove leftover use of log_id
2026-06-24 08:04:48 +02:00
KrystalDelusion
a07c484ce1
Merge pull request #5981 from YosysHQ/krys/equiv_opt_unknown
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equiv_opt: Add ignore-unknown-cells
2026-06-23 19:58:30 +00:00
Miodrag Milanovic
a689342207
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a
End of file fix
2026-06-23 07:23:41 +02:00
Krystine Sherwin
de6aa77dc8
equiv_opt: Add ignore-unknown-cells
2026-06-23 10:54:00 +12:00
nella
3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index
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Optimize upto vector indexing (Fix #892 ).
2026-06-22 09:05:26 +00:00
nella
6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup
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Add warnings and errors to `sim -r` with VCD code path
2026-06-22 09:02:32 +00:00
nella
2195277b5a
Merge pull request #5960 from YosysHQ/nella/latch-infer
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proc_dlatch - infer $adlatch (Fix #5910 ).
2026-06-18 16:50:48 +00:00
nella
c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745
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Fix `chparam` values are unsigned when using read_verilog frontend
2026-06-18 16:50:22 +00:00
nella
46cbeab720
Add effort limit.
2026-06-18 11:58:01 +02:00
nella
75a30a22d6
Cleanup bitsim, document hypo.
2026-06-18 11:43:13 +02:00
nella
25810193ab
Reuse sat/hashlib.
2026-06-18 10:57:20 +02:00
nella
a5bdb29d7f
Recognise asynchronous set/reset.
2026-06-15 15:44:50 +02:00
Emil J. Tywoniak
6032b064e2
opt_muxtree: optimize for single driver, error on multiple drivers
2026-06-15 15:08:26 +02:00
nella
05805e8b93
Merge pull request #5900 from YosysHQ/nella/arith_tree_improvements
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arith_tree improvements
2026-06-12 14:23:10 +00:00
nella
309b7d2496
Verify kogge stone impl.
2026-06-12 14:55:47 +02:00
nella
135c2a4113
Get rid of normalize_to_width.
2026-06-11 01:12:35 +02:00
nella
d52670e58b
Replace suitable (2^k-1)-x with ~x.
2026-06-10 11:29:55 +02:00
Lofty
c96d7bc998
Merge pull request #5943 from YosysHQ/lofty/abc9-refactor-6
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move `abc9_ops -reintegrate` into its own pass
2026-06-08 12:57:08 +00:00
nella
c47ed4bc31
Fix help.
2026-06-08 13:47:56 +02:00
nella
3c6900a570
Depth-schedule finar adder.
2026-06-08 13:47:56 +02:00
nella
f8d2252735
Use ripple as default final adder, gate fma.
2026-06-08 13:47:56 +02:00
nella
d40431f249
Remove black boxes for now.
2026-06-08 13:29:05 +02:00
nella
5e4e5a1d40
Arith tree - parallel prefix.
2026-06-08 13:29:05 +02:00
nella
862e9fc54e
Remove elarith-fast for now.
2026-06-08 13:29:05 +02:00
nella
25eb394ad0
Collapse signed*signed or combined nodes via BW.
2026-06-08 13:29:05 +02:00
nella
bc07c6b1b0
Improve arith_tree: FMA add, elarith WIP.
2026-06-08 13:29:05 +02:00
Lofty
0e32ad7eed
move abc9_ops -reintegrate into its own pass
2026-06-08 11:03:17 +01:00
Miodrag Milanovic
102f008194
Remove EMSCRIPTEN leftovers
2026-06-05 10:03:27 +02:00
Miodrag Milanović
693d5a7eb0
Merge pull request #5903 from YosysHQ/krys/verific_memsize
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verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
2026-06-04 05:43:04 +00:00
Miodrag Milanovic
a599999d1f
Fixed warnings found by gcc-16
2026-06-03 13:09:38 +02:00
Catherine
afc0e78d11
Update top-level Python project for CMake compatibility.
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This commit reimplements the (no longer recommended) setuptools based
build system using a standards-based in-tree PEP517 build backend.
The implementation is partially based on
https://codeberg.org/ziglang/zig-pypi/src/branch/main/make_wheels.py
which is licensed under BSD-0-clause.
It also adds a new option `YOSYS_BUILD_PYTHON_ONLY` that is available
only if the binary or the library aren't going to be installed, which
turns off these targets entirely, as well as some dependent ones
(e.g. tests).
Co-authored-by: Mohamed Gaber <me@donn.website>
2026-06-03 09:03:23 +00:00
Catherine
a727e7f6e7
Migrate build system to CMake
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See #5895 for details.
This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
Philippe Sauter
c89cfe1e6e
peepopt: add shiftpow2 pattern
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Rewrite power-of-two indexed word selects to $bmux when the shift
amount already carries the scale as low zero bits.
Keep the rule to non-overlapping selections and bound the generated
mux ways. Add regressions for aligned shifts, padding, signed
extension, and shiftmul handoff cases.
2026-05-31 02:01:32 +02:00
Krystine Sherwin
f6327cc444
check_mem: Add -non-const option
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Can identify potentially dangerous addressing, but also prone to false-positives.
2026-05-29 18:40:24 +12:00
Krystine Sherwin
07e3d648aa
Add check_mem command
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Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878 .
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands. Helpful for when you want to run the same set of commands on a bunch of sv files.
2026-05-29 18:40:23 +12:00
KrystalDelusion
4230ebff71
Merge pull request #5912 from YosysHQ/krys/opt_clean_docs
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opt_clean: Set group for docs gen
2026-05-28 08:35:52 +00:00
Krystine Sherwin
680bb69d85
opt_clean: Set group for docs gen
2026-05-28 14:50:11 +12:00
junyao
6f111118de
proc: ignore nosync temporaries in always_latch checks
2026-05-26 00:56:07 +08:00
nella
68df0be7d2
Remove eqbits flag.
2026-05-25 14:16:55 +02:00
nella
386e63ae20
Add prepass for bit simulation.
2026-05-25 12:49:29 +02:00
nella
bbec8d2902
Gate behind flag.
2026-05-20 16:44:52 +02:00
nella
c6bf13bb94
Implement worklist and SAT counterexample splitting.
2026-05-20 16:44:52 +02:00
nella
d85e3f10de
Add tests.
2026-05-20 16:44:52 +02:00
nella
f69a5fc077
Elim equiv bits.
2026-05-20 16:44:52 +02:00
nella
886d0a7043
Merge branch 'main' into gus/sim-with-vcd-tuneup
2026-05-19 12:17:29 +02:00
nella
44a1abdade
Don't repeat VCD warnings + fixups.
2026-05-19 12:16:29 +02:00
Miodrag Milanovic
2159a0e634
Remove file added by mistake
2026-05-18 17:00:16 +02:00
