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Code Activity
15576 commits 122 branches 59 tags 73 MiB
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2121 commits

Author SHA1 Message Date
Eddie Hung
e7a8cdbccf Add shregmap -tech xilinx test 2019-08-22 16:16:54 -07:00
Eddie Hung
698a0e3aaf WIP for equivalency checking memories 2019-08-22 16:05:12 -07:00
Eddie Hung
43e7c4917a Do not print OKAY 2019-08-22 16:05:12 -07:00
Eddie Hung
5061d239ae Fail if iverilog fails 2019-08-22 16:05:12 -07:00
Eddie Hung
8e3754bdb4 Hide tri-state warning message for now 2019-08-22 16:05:12 -07:00
Eddie Hung
659a481482 Remove unused output 2019-08-22 16:05:12 -07:00
Eddie Hung
61087329ef Fix tribuf test 2019-08-22 16:05:12 -07:00
Eddie Hung
f9906eed68 Fix comments 2019-08-22 16:05:12 -07:00
Eddie Hung
9224b3bc17 Remove tech independent synthesis 2019-08-22 16:05:12 -07:00
Eddie Hung
388eb3288c Remove dffe instantation 2019-08-22 16:04:50 -07:00
Eddie Hung
9e537a76b5 Move $dffe to dffs.{v,ys} 2019-08-22 16:04:48 -07:00
Eddie Hung
c5754d9e8b Make multiplier wider, do not do tech independent synth 2019-08-22 16:04:07 -07:00
Eddie Hung
b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx 
opt_expr to trim A port of $shiftx/$shift
 2019-08-22 10:31:27 -07:00
Eddie Hung
6f971470f8 Respect opt_expr -keepdc as per @cliffordwolf 2019-08-22 08:37:27 -07:00
Eddie Hung
379f33af54 Handle $shift and Y_WIDTH > 1 as per @cliffordwolf 2019-08-22 08:22:23 -07:00
Eddie Hung
bb1a8a0190 Add test 2019-08-21 21:58:20 -07:00
Eddie Hung
a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
SergeyDegtyar
d945b8a357 Fix all comments from PR 2019-08-21 21:52:07 +03:00
SergeyDegtyar
b835ec37cb Add temp directory 2019-08-21 07:53:34 +03:00
Eddie Hung
fce8dc7db2 Add test 2019-08-20 20:05:16 -07:00
SergeyDegtyar
71dd412ac5 Fix tests; Remove simulation; 
- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
 2019-08-20 15:52:25 +03:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00
Clifford Wolf
6ffb910d12 Add test case for real parameters 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-20 11:38:21 +02:00
SergeyDegtyar
153ec0541c Add new tests for ice40 architecture 2019-08-20 07:50:05 +03:00
whitequark
4a942ba7b9 proc_clean: fix order of switch insertion. 
Fixes #1268.
 2019-08-19 16:44:23 +00:00
Clifford Wolf
21699e5840 Add *.sv to tests/simple_abc9/.gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-19 13:04:57 +02:00
Clifford Wolf
1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00
Eddie Hung
e34f2de55d Merge remote-tracking branch 'origin/master' into clifford/testfast 2019-08-18 21:29:15 -07:00
Eddie Hung
f5170a7eda Removal of more stat calls from tests 2019-08-18 21:28:45 -07:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again 2019-08-18 08:04:10 +00:00
Clifford Wolf
9e940f1276 Speed up "make test" and related cleanups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:37:07 +02:00
Clifford Wolf
f20be90436 Add test for pmtest_test "reduce" demo pattern 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:05:10 +02:00
Eddie Hung
51d28645da Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share 2019-08-16 13:40:29 -07:00
Clifford Wolf
40c40d9f5d Do not use Verific in tests/various/write_gzip.ys 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 14:22:46 +02:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung
88d5185596 Merge remote-tracking branch 'origin/master' into eddie/fix_1262 2019-08-11 21:13:40 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung
0adf81cb91 Add $alu tests 2019-08-09 12:13:17 -07:00
Eddie Hung
8350dfb809 Add alumacc versions of opt_expr tests 2019-08-09 10:30:53 -07:00
Eddie Hung
9300111601 Add new $alu test, remove wreduce 2019-08-09 10:22:06 -07:00
Eddie Hung
313c9ec8df Cleanup some more 2019-08-09 10:13:49 -07:00
Eddie Hung
d9c1664462 Simplify opt_expr tests using equiv_opt 2019-08-09 10:08:17 -07:00
Eddie Hung
8bf45f34c4 Remove dump call 2019-08-07 21:36:02 -07:00
Eddie Hung
2b6cdfb39f Move tests/various/opt* into tests/opt/ 2019-08-07 21:35:48 -07:00
Eddie Hung
d5e8c0e6d3 Remove ice40_unlut call, simply do equiv_opt on synth_ice40 2019-08-07 21:33:56 -07:00
Eddie Hung
35bf509603 Add testcase from removed opt_ff.{v,ys} 2019-08-07 21:31:32 -07:00
Eddie Hung
4545bf482f Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run 2019-08-07 16:48:38 -07:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add 
wreduce/opt_expr: improve width reduction for $add and $sub cells
 2019-08-07 14:27:35 +02:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor 
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
 2019-08-07 12:31:32 +02:00
Bogdan Vukobratovic
067b44938c Fix wrong results when opt_share called before opt_clean 2019-08-07 09:30:58 +02:00