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Add shregmap -tech xilinx test

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Eddie Hung 2019-06-12 08:34:06 -07:00
parent 8691596d19
commit e7a8cdbccf
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tests/various/shregmap.ys
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@ -64,3 +64,4 @@ sat -verify -prove-asserts -show-ports -seq 5 miter
# design -load gate
# stat