mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-26 09:24:37 +00:00
Code Activity
15872 commits 122 branches 59 tags 72 MiB
Commit graph

2006 commits

Author SHA1 Message Date
Clifford Wolf
584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-29 16:32:44 +01:00
Clifford Wolf
7682629b79 Add "read -verific" and "read -noverific" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-27 14:03:35 +01:00
Clifford Wolf
c863796e9f Fix "verific -extnets" for more complex situations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 14:17:46 +01:00
Clifford Wolf
638be461c3 Fix mem2reg handling of memories with upto data ports, fixes #888 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:21:17 +01:00
Clifford Wolf
da42f10765 Improve "read_verilog -dump_vlog[12]" handling of upto ranges 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:20:16 +01:00
Clifford Wolf
9b0e7af6d7 Improve read_verilog debug output capabilities 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 20:52:29 +01:00
Eddie Hung
02e8dc7ad2 Merge https://github.com/YosysHQ/yosys into read_aiger 2019-03-19 08:52:31 -07:00
Eddie Hung
3e89cf68bd Add author name 2019-03-19 08:52:06 -07:00
Zachary Snow
a5f4b83637 fix local name resolution in prefix constructs 2019-03-18 20:43:20 -04:00
Clifford Wolf
17caaa3fa8 Improve handling of "full_case" attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 17:51:21 +01:00
Clifford Wolf
d25a0c8ade Improve handling of memories used in mem index expressions on LHS of an assignment 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:12:02 +01:00
Clifford Wolf
a4ddc569b4 Remove outdated "blocking assignment to memory" warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:10:55 +01:00
Clifford Wolf
ab5b50ae3c Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:09:47 +01:00
Clifford Wolf
b02d9c2634 Fix handling of cases that look like sva labels, fixes #862 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-10 16:27:18 -07:00
Clifford Wolf
cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels 
Add support for using SVA labels in yosys-smtbmc console output
 2019-03-09 11:14:57 -08:00
Clifford Wolf
e7a34d342e Also add support for labels on sva module items, fixes #699 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-08 22:55:09 -08:00
Eddie Hung
ee013fba54 Update help message for -chparam 2019-03-09 01:56:16 +00:00
Eddie Hung
2aa3903757 Add -chparam option to verific command 2019-03-09 01:54:01 +00:00
Eddie Hung
1dc060f32e Fix spelling 2019-03-09 00:43:50 +00:00
Clifford Wolf
a330c68363 Fix handling of task output ports in clocked always blocks, fixes #857 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 22:44:37 -08:00
Clifford Wolf
22ff60850e Add support for SVA labels in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:17:32 -08:00
Clifford Wolf
cda37830b0 Add hack for handling SVA labels via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 10:52:44 -08:00
Clifford Wolf
52f80718a7
Merge pull request #848 from YosysHQ/clifford/fix763 
Fix error for wire decl in always block, fixes 763
 2019-03-02 16:32:58 -08:00
Clifford Wolf
ae9286386d Only run derive on blackbox modules when ports have dynamic size 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 12:36:46 -08:00
Clifford Wolf
3a51714451 Fix error for wire decl in always block, fixes #763 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 11:56:44 -08:00
Clifford Wolf
ce6695e22c Fix $global_clock handling vs autowire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 10:38:13 -08:00
Clifford Wolf
5d93dcce86 Fix $readmem[hb] for mem2reg memories, fixes #785 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 09:58:20 -08:00
Clifford Wolf
7cfae2c52f Use mem2reg on memories that only have constant-index write ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 13:35:09 -08:00
Clifford Wolf
60e3c38054 Improve "read" error msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-28 20:34:42 -08:00
Eddie Hung
f7c7003a19 Merge remote-tracking branch 'origin/master' into xaig 2019-02-26 13:16:03 -08:00
Eddie Hung
da076344cc parse_xaiger() to really pass single and multi-bit inout tests 2019-02-26 12:04:45 -08:00
Eddie Hung
8f02c846f6 parse_xaiger() to cope with multi bit inouts 2019-02-26 11:37:34 -08:00
Eddie Hung
316232a7dd parse_xaiger() to untransform $inout.out output ports 2019-02-25 18:40:23 -08:00
Eddie Hung
721f6a14fb read_aiger to accept empty string for clk_name, passable only if no latches 2019-02-25 15:34:02 -08:00
Clifford Wolf
1816fe06af Fix handling of defparam for when default_nettype is none 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:09:41 +01:00
Clifford Wolf
a516b4fb5a Check if Verific was built with DB_PRESERVE_INITIAL_VALUE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 19:51:30 +01:00
Eddie Hung
07036b8bf7 read_aiger to work with symbol table 2019-02-21 17:01:07 -08:00
Eddie Hung
085ed9f487 Add attribution 2019-02-21 14:40:13 -08:00
Eddie Hung
3307295488 Merge branch 'read_aiger' into xaig 2019-02-21 14:27:32 -08:00
Clifford Wolf
23148ffae1 Fixes related to handling of autowires and upto-ranges, fixes #814 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 18:40:11 +01:00
Clifford Wolf
974927adcf Fix handling of expression width in $past, fixes #810 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:55:33 +01:00
Clifford Wolf
28fba903c5 Fix segfault in printing of some internal error messages 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:40:52 +01:00
Eddie Hung
9e299a0908 read_aiger to not do -purge for clean 2019-02-20 17:33:04 -08:00
Eddie Hung
32853b1f8d lut/not/and suffix to be ${lut,not,and} 2019-02-20 16:30:30 -08:00
Eddie Hung
abc1c2672e read_aiger to also rename 0 index lut when wideports 2019-02-20 16:17:22 -08:00
Eddie Hung
f9702a8abe read_aiger: new naming fixes 2019-02-20 12:39:51 -08:00
Eddie Hung
83b66861e9 read_aiger to name wires with internal name, less likely to clash 2019-02-20 11:22:56 -08:00
Eddie Hung
7b026c4bc3 Same for ascii AIGERs too 2019-02-19 15:15:50 -08:00
Eddie Hung
d304882cba read_aiger to cope with non-unique POs 2019-02-19 15:14:08 -08:00
Eddie Hung
e79df5e70e read_aiger to create sane $lut names, and rename when renaming driving wire 2019-02-19 12:27:50 -08:00