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read_aiger to accept empty string for clk_name, passable only if no latches

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This commit is contained in:
Eddie Hung 2019-02-25 15:34:02 -08:00
parent 0ca3fd6a1c
commit 721f6a14fb
2 changed files with 3 additions and 2 deletions
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2
frontends/aiger/aigerparse.cc
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@ -524,6 +524,7 @@ void AigerReader::parse_aiger_ascii()
// Parse latches
RTLIL::Wire *clk_wire = nullptr;
if (L > 0) {
log_assert(clk_name != "");
clk_wire = module->wire(clk_name);
log_assert(!clk_wire);
log_debug("Creating %s\n", clk_name.c_str());
@ -654,6 +655,7 @@ void AigerReader::parse_aiger_binary()
// Parse latches
RTLIL::Wire *clk_wire = nullptr;
if (L > 0) {
log_assert(clk_name != "");
clk_wire = module->wire(clk_name);
log_assert(!clk_wire);
log_debug("Creating %s\n", clk_name.c_str());