132 commits

Author	SHA1	Message	Date
Clifford Wolf	f7bd0a5232	Use log_abort() and log_assert() in BTOR backend	2014-03-07 15:56:10 +01:00
Clifford Wolf	337b461d26	Added $lut support to blif backend (by user eddiehung from reddit)	2014-02-22 14:25:32 +01:00
Clifford Wolf	038eac7414	Better handling of nameDef and nameRef in edif backend	2014-02-21 13:40:43 +01:00
Clifford Wolf	f3ff29d410	Fixed instantiating multi-bit ports in edif backend	2014-02-21 13:10:36 +01:00
Clifford Wolf	79f8944811	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	2014-02-21 10:40:15 +01:00
Ahmed Irfan	ac896c63e2	modified btor synthesis script for correct use of splice command.	2014-02-12 13:38:28 +01:00
Ahmed Irfan	45e468114a	disabling splice command in the script	2014-02-11 15:43:03 +01:00
Ahmed Irfan	1d64b3e008	register output corrected	2014-02-11 13:28:05 +01:00
Ahmed Irfan	e8f6b8f201	added concat and slice cell translation	2014-02-11 13:06:01 +01:00
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	f4f230d7cc	Fixed gcc compiler warnings with release build	2014-02-06 22:49:14 +01:00
Clifford Wolf	583636f0ad	Added BTOR backend README file	2014-02-05 18:31:10 +01:00
Clifford Wolf	968ae31cac	Added support for dump -append	2014-02-04 23:45:30 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	fa103e55ad	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys	2014-01-26 02:29:19 +01:00
Johann Glaser	f13b3518aa	beautified write_intersynth	2014-01-25 20:16:38 +01:00
Ahmed Irfan	0325efe172	root bug corrected	2014-01-25 19:33:24 +01:00
Ahmed Irfan	137742786e	removed regex include	2014-01-24 18:04:37 +01:00
Ahmed Irfan	2e44b1b73a	merged clifford changes + removed regex	2014-01-24 17:35:42 +01:00
Clifford Wolf	210dda286f	Use techmap -share_map in btor scripts	2014-01-24 15:52:16 +01:00
Clifford Wolf	6804edd5d4	Moved btor scripts to backends/btor/	2014-01-24 15:48:07 +01:00
Ahmed Irfan	aa3cb20e1e	slice bug corrected	2014-01-20 18:35:52 +01:00
Ahmed Irfan	c347f2825f	assert feature	2014-01-20 10:45:02 +01:00
Ahmed Irfan	9a689f33a5	verilog default options pull ... shift operator width issues	2014-01-17 19:32:35 +01:00
Ahmed Irfan	c7a2e582aa	slice error corrected	2014-01-16 20:16:01 +01:00
Ahmed Irfan	3a1490888d	width issues ... dff cell for more than one registers	2014-01-15 17:36:33 +01:00
Ahmed Irfan	661b5a993e	BTOR backend	2014-01-14 12:03:53 +01:00
Ahmed Irfan	06482c046b	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	2014-01-03 10:54:54 +01:00
Ahmed Irfan	ffd768ce86	btor	2014-01-03 10:52:44 +01:00
Clifford Wolf	74d0de3b74	Updated manual/command-reference-manual.tex	2013-12-28 12:14:47 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	b5afd75b0a	Fixed gentb_constant handling in autotest backend	2013-12-04 09:09:42 +01:00
Clifford Wolf	ed441346ca	Added dump -m and -n options	2013-11-29 10:33:36 +01:00
Clifford Wolf	41205afc39	Added proper dumping of signed/unsigned parameters to verilog backend	2013-11-24 17:47:22 +01:00
Clifford Wolf	0ef22c7609	Added support for signed parameters in ilang	2013-11-24 17:37:27 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	1e6836933d	Added modelsim support to autotest	2013-11-24 15:10:43 +01:00
Clifford Wolf	28093d9dd2	Added "top" attribute to mark top module in hierarchy	2013-11-24 05:03:43 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	40d9542647	Implemented $_DFFSR_ expression generator in verilog backend	2013-11-21 21:52:30 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	2864cb3b59	Silenced a gcc warning in spice backend	2013-11-09 12:01:50 +01:00
Clifford Wolf	ba305a7ca6	Improved comments on topological sort in edif backend	2013-11-04 08:34:15 +01:00
Clifford Wolf	cd0fe7d786	Added simple topological sort to edif backend	2013-11-03 22:01:32 +01:00
Clifford Wolf	1dcb683fcb	Write yosys version to output files	2013-11-03 21:41:39 +01:00
Clifford Wolf	eab536a203	Merge branch 'master' of github.com:cliffordwolf/yosys	2013-11-03 21:13:21 +01:00
Clifford Wolf	4a60e5842d	Ignore explicit unconnected ports in intersynth backend	2013-11-03 09:00:51 +01:00
Clifford Wolf	0efe16f118	Added placeholder check to dfflibmap and cleaned up some other placeholder checks	2013-10-31 12:27:07 +01:00