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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)

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This commit is contained in:
Clifford Wolf 2014-02-03 13:01:45 +01:00
parent de9226a64f
commit a6750b3753
11 changed files with 186 additions and 78 deletions
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4
backends/btor/btor.cc
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@ -716,6 +716,8 @@ struct BtorDumper
else if(cell->type == "$memrd")
{
log("writing memrd cell\n");
if (cell->parameters.at("\\CLK_ENABLE").as_bool() == true)
log_error("The btor backen does not support $memrd cells with built-in registers. Run memory_dff with -wr_only.\n");
str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
@ -729,6 +731,8 @@ struct BtorDumper
else if(cell->type == "$memwr")
{
log("writing memwr cell\n");
if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
int clk = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1);
bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
int enable = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\EN")), 1);

3
backends/btor/verilog2btor.sh
View file

@ -25,7 +25,8 @@ proc;
opt; opt_const -mux_undef; opt;
rename -hide;;;
techmap -share_map pmux2mux.v;;
memory -nomap;;
memory_dff -wr_only
memory_collect;;
flatten;;
memory_unpack;
splitnets -driver;