Eddie Hung
e301440a0b
Use attributes instead of params
2019-08-19 09:51:49 -07:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
562c9e3624
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
2019-08-16 15:40:53 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Marcin Kościelnicki
49765ec19e
minor review fixes
2019-08-13 18:05:49 +00:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
...
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Eddie Hung
66806085db
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
David Shah
ab607e896e
xilinx: Fix missing cell name underscore in cells_map.v
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-25 08:19:07 +01:00
Eddie Hung
43616e1414
Update Makefile too
2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
Eddie Hung
1c9f3fadb9
Add Tsu offset to boxes, and comments
2019-07-11 17:17:26 -07:00
Eddie Hung
d386177e6d
ABC doesn't like negative delays in flop boxes...
2019-07-11 17:09:17 -07:00
Eddie Hung
3ef927647c
Fix FDCE_1 box
2019-07-11 14:25:47 -07:00
Eddie Hung
1ada568134
Revert "$pastQ should be first input"
...
This reverts commit 8f9d529929
2019-07-11 14:23:45 -07:00
Eddie Hung
854333f2af
Propagate INIT attr
2019-07-11 13:55:47 -07:00
Eddie Hung
8f9d529929
$pastQ should be first input
2019-07-11 13:54:40 -07:00
Eddie Hung
021f8e5492
Fix typo
2019-07-11 13:23:07 -07:00
Eddie Hung
19c1c3cfa3
Merge pull request #1182 from koriakin/xc6s-bram
...
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 12:55:35 -07:00
Marcin Kościelnicki
a9efacd01d
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
Eddie Hung
8fef4c3594
Simplify to $__ABC_ASYNC box
2019-07-11 10:52:33 -07:00
Eddie Hung
93fbd56db1
$__ABC_FD_ASYNC_MUX.Q -> Y
2019-07-11 10:25:59 -07:00
Marcin Kościelnicki
ce250b341c
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
Eddie Hung
d357431df1
Restore from master
2019-07-10 22:54:39 -07:00
Eddie Hung
f984e0cb34
Another typo
2019-07-10 22:33:35 -07:00
Eddie Hung
ea6ffea2cd
Fix clk_pol for FD*_1
2019-07-10 20:10:20 -07:00
Eddie Hung
7899a06ed6
Another typo
2019-07-10 19:59:24 -07:00
Eddie Hung
ad35b509de
Another typo
2019-07-10 19:05:53 -07:00
Eddie Hung
f3511e4f93
Use \$currQ
2019-07-10 19:01:13 -07:00
Eddie Hung
f030be3f1c
Preserve all parameters, plus some extra ones for clk/en polarity
2019-07-10 18:57:11 -07:00
Eddie Hung
4a995c5d80
Change how to specify flops to ABC again
2019-07-10 17:54:56 -07:00
Eddie Hung
3bb48facb2
Remove params from FD*_1 variants
2019-07-10 17:17:54 -07:00
Eddie Hung
0372c900e8
Fix typo, and have !{PRE,CLR} behave as CE
2019-07-10 17:15:49 -07:00
Eddie Hung
7b2599cb94
Move ABC FF stuff to abc_ff.v; add support for other FD* types
2019-07-10 17:06:05 -07:00
Eddie Hung
0ab8f28bc7
Uncomment IS_C_INVERTED parameter
2019-07-10 16:23:15 -07:00
Eddie Hung
838ae1a14c
synth_xilinx's map_cells stage to techmap ff_map.v
2019-07-10 16:15:57 -07:00
Eddie Hung
73c8f1a59e
Fix box numbering
2019-07-10 16:12:33 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
Eddie Hung
bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
...
Error out if -abc9 and -retime specified
2019-07-10 14:38:13 -07:00
Eddie Hung
6bbd286e03
Error out if -abc9 and -retime specified
2019-07-10 12:47:48 -07:00
Eddie Hung
58bb84e5b2
Add some spacing
2019-07-10 12:32:33 -07:00
Eddie Hung
521971e32e
Add some ASCII art explaining mux decomposition
2019-07-10 12:20:04 -07:00
Eddie Hung
e573d024a2
Call muxpack and pmux2shiftx before cmp2lut
2019-07-09 21:26:38 -07:00
Eddie Hung
c55530b901
Restore opt_clean back to original place
2019-07-09 14:29:58 -07:00
Eddie Hung
5b48b18d29
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
2019-07-09 14:28:54 -07:00
Eddie Hung
b1a048a703
Extend using A[1] to preserve don't care
2019-07-09 12:35:41 -07:00
Eddie Hung
93522b0ae1
Extend during mux decomposition with 1'bx
2019-07-09 10:59:37 -07:00
Eddie Hung
c864995343
Fix typo and comments
2019-07-09 10:38:07 -07:00
Eddie Hung
c91cb73562
Merge remote-tracking branch 'origin/master' into xc7mux
2019-07-09 10:22:49 -07:00
