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A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. |
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| .. | ||
| tests | ||
| .gitignore | ||
| abc_xc7.box | ||
| abc_xc7.lut | ||
| abc_xc7_nowide.lut | ||
| arith_map.v | ||
| brams_init.py | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.sh | ||
| cells_xtra.v | ||
| drams.txt | ||
| drams_map.v | ||
| ff_map.v | ||
| lut_map.v | ||
| Makefile.inc | ||
| mux_map.v | ||
| synth_xilinx.cc | ||
| xc6s_brams.txt | ||
| xc6s_brams_bb.v | ||
| xc6s_brams_map.v | ||
| xc7_brams.txt | ||
| xc7_brams_bb.v | ||
| xc7_brams_map.v | ||