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Author	SHA1	Message	Date
Eddie Hung	1c0ee4f786	Do not replace constants with same wire	2019-11-27 08:18:41 -08:00
Eddie Hung	6464dc35ec	Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd ... xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder	2019-11-27 08:00:22 -08:00
Clifford Wolf	41e0ddf4f4	Merge pull request #1501 from YosysHQ/dave/mem_copy_attr ... memory_collect: Copy attr from RTLIL::Memory to cell	2019-11-27 11:25:23 +01:00
Clifford Wolf	f43c0bd8ba	Merge pull request #1534 from YosysHQ/mwk/opt_share-fix ... opt_share: Fix handling of fine cells.	2019-11-27 11:23:16 +01:00
Eddie Hung	95053d9010	Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve ... write_xaiger improvements	2019-11-27 01:04:29 -08:00
Eddie Hung	f6c0ec1d09	Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff	2019-11-27 01:03:33 -08:00
Eddie Hung	4ba6f4f0d7	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-27 01:02:21 -08:00
Eddie Hung	6338615aa1	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-27 01:02:16 -08:00
Eddie Hung	c7aa2c6b79	Cleanup	2019-11-27 01:01:24 -08:00
Eddie Hung	cb05fe0f70	Check for nullptr	2019-11-27 00:51:39 -08:00
Eddie Hung	d960feeeb0	Stray log_dump	2019-11-27 00:50:25 -08:00
Eddie Hung	8c813632b6	Revert "submod to bitty rather bussy, for bussy wires used as input and output" ... This reverts commit cba3073026.	2019-11-27 00:48:22 -08:00
Eddie Hung	969f511415	Promote output wires in sigmap so that can be detected	2019-11-26 23:39:14 -08:00
Eddie Hung	6318e3ce6d	Fix wire width	2019-11-26 23:38:49 -08:00
Eddie Hung	5e487b103c	Fix submod -hidden	2019-11-26 23:26:25 -08:00
Eddie Hung	435d33c373	Add -hidden option to submod	2019-11-26 23:26:12 -08:00
Eddie Hung	de3476cc23	No need for -abc9	2019-11-26 23:08:14 -08:00
Marcin Kościelnicki	fdcbda195b	opt_share: Fix handling of fine cells. ... Fixes #1525.	2019-11-27 08:01:07 +01:00
Eddie Hung	5e67df38ed	latch -> box	2019-11-26 22:59:05 -08:00
Eddie Hung	f1538c3642	Merge branch 'master' into xaig_dff	2019-11-26 22:56:53 -08:00
Eddie Hung	4a0198128e	Add citation	2019-11-26 22:51:16 -08:00
Eddie Hung	2105ae176a	Check for either sign or zero extension for postAdd packing	2019-11-26 22:51:00 -08:00
Eddie Hung	15042eaf57	Remove notes	2019-11-26 22:41:35 -08:00
Eddie Hung	a30d5e1cc3	Fold loop	2019-11-26 21:57:50 -08:00
Eddie Hung	68717dd03b	Do not sigmap keep bits inside write_xaiger	2019-11-26 21:57:50 -08:00
Eddie Hung	7136cee6b4	xaiger: do not promote output wires	2019-11-26 21:55:37 -08:00
Eddie Hung	222e199b73	Add testcase derived from fastfir_dynamictaps benchmark	2019-11-26 21:26:30 -08:00
Eddie Hung	99702efaba	xaiger: do not promote output wires	2019-11-26 19:03:02 -08:00
Eddie Hung	739f530906	Move 'clean' from map_luts to finalize	2019-11-26 14:51:39 -08:00
Eddie Hung	09637dd3e4	Fix submod -hidden	2019-11-26 11:57:26 -08:00
Eddie Hung	3027f015c2	clkpart to use 'submod -hidden'	2019-11-26 11:35:32 -08:00
Eddie Hung	e8aa92ca35	Add -hidden option to submod	2019-11-26 11:35:15 -08:00
Eddie Hung	eb666b4677	Update docs with bullet points	2019-11-26 11:12:58 -08:00
Marcin Kościelnicki	0466c48533	xilinx: Add simulation models for IOBUF and OBUFT.	2019-11-26 08:15:20 +01:00
Eddie Hung	0d7ba77426	Move \init from source wire to submod if output port	2019-11-25 16:07:47 -08:00
Eddie Hung	dd317c9280	Add testcase where \init is copied	2019-11-25 16:07:35 -08:00
Eddie Hung	da51492dbc	Fold loop	2019-11-25 15:43:37 -08:00
Eddie Hung	7f0914a408	Do not sigmap keep bits inside write_xaiger	2019-11-25 15:42:07 -08:00
Eddie Hung	67be62a957	clkpart to analyse async flops too	2019-11-25 13:39:37 -08:00
Eddie Hung	6831510f5b	Fix debug	2019-11-25 12:59:34 -08:00
Eddie Hung	d087024caf	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-25 12:42:09 -08:00
Eddie Hung	6a2eb5d8f9	Special abc9_clock wire to contain only clock signal	2019-11-25 12:36:13 -08:00
Eddie Hung	180cb39395	abc9 to contain time call	2019-11-25 12:35:57 -08:00
Eddie Hung	f50b6422b0	abc9 to no longer to clock partitioning, operate on whole modules only	2019-11-25 12:35:38 -08:00
Eddie Hung	63b7a48fbc	clkpart to analyse async flops too	2019-11-25 12:04:11 -08:00
Marcin Kościelnicki	6cdea425b8	clkbufmap: Add support for inverters in clock path.	2019-11-25 20:40:39 +01:00
Marcin Kościelnicki	7562e7304e	xilinx: Use INV instead of LUT1 when applicable	2019-11-25 20:40:39 +01:00
Pepijn de Vos	72d03dc910	attempt to fix formatting	2019-11-25 14:50:34 +01:00
Pepijn de Vos	6c79abbf5a	gowin: add and test dff init values	2019-11-25 14:33:21 +01:00
Eddie Hung	23ecf12bbf	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-23 10:29:03 -08:00