2471 commits

Author	SHA1	Message	Date
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	b17d6531c8	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
Clifford Wolf	f1ca93a0a3	Fixed simlib.v model for $mem	2014-07-17 16:48:36 +02:00
Clifford Wolf	dcdd5c11b4	Updated simlib to new $mem/$memwr interface	2014-07-16 11:46:40 +02:00
Clifford Wolf	7370ae01e9	Added SIMLIB_NOLUT to simlib.v	2014-04-02 21:28:33 +02:00
Clifford Wolf	e24797add0	Added SIMLIB_NOSR to simlib.v	2014-04-02 21:06:55 +02:00
Clifford Wolf	d4a1b0af5b	Added support for dlatchsr cells	2014-03-31 14:14:40 +02:00
Clifford Wolf	7aa2d746b7	Merged addition of SED makefile variable from github.com/Siesh1oo/yosys ... (see https://github.com/cliffordwolf/yosys/pull/28)	2014-03-11 14:42:58 +01:00
Clifford Wolf	973507d85b	Fixes for improved techmap of shifts with large B inputs	2014-03-06 13:33:12 +01:00
Clifford Wolf	8406e7f7b6	Strictly zero-extend unsigned A-inputs of shift operations in techmap	2014-03-06 12:15:44 +01:00
Clifford Wolf	d7f29bb23f	Improved techmap of shift with wide B inputs	2014-03-06 12:14:20 +01:00
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	ed8ad99960	More changes to techlibs/common/simlib.v for LEC	2014-01-31 11:21:29 +01:00
Clifford Wolf	6a7d7e847d	Added test comments to techlibs/cmos/cmos_cells.lib	2014-01-29 10:51:02 +01:00
Clifford Wolf	a86f33653d	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	2014-01-29 00:36:03 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	3d7a1491aa	Fixed $lut simlib model for a wider range of tools	2014-01-18 19:31:40 +01:00
Clifford Wolf	2fbaaaca7a	More changes to simlib to make it friendlier to a wider range of tools	2014-01-18 19:13:43 +01:00
Clifford Wolf	4a9e133fab	Fixed a type in $mem model in simlib.v	2014-01-18 18:54:50 +01:00
Clifford Wolf	bef17eeb10	Removed cases of trailing comma in stdcells.v	2014-01-18 15:36:17 +01:00
Clifford Wolf	5b96675696	Added $bu0 cell to simlib.v	2014-01-18 15:35:15 +01:00
Clifford Wolf	db9cf544b8	Added techlibs/common/pmux2mux.v	2014-01-17 20:06:15 +01:00
Clifford Wolf	b3b00f1bf4	Various small cleanups in stdcells.v techmap code	2013-12-31 15:41:40 +01:00
Clifford Wolf	c69c416d28	Added $bu0 cell (for easy correct $eq/$ne mapping)	2013-12-28 12:02:14 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	76f7c10cfc	Using simplemap mappers from techmap	2013-11-24 23:31:14 +01:00
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00
Clifford Wolf	20175afd29	Added "techmap -share_map" option	2013-11-24 19:50:25 +01:00
Clifford Wolf	ae798d3fd5	Fixed xilinx/example_sim_counter test bench	2013-11-24 17:55:46 +01:00
Clifford Wolf	532091afcb	Added more generic _TECHMAP_ wire mechanism to techmap pass	2013-11-23 15:58:06 +01:00
Clifford Wolf	1c4a6411af	Updated abc	2013-11-21 22:39:10 +01:00
Clifford Wolf	0c91f890c9	Install simlib in datdir	2013-11-19 23:05:46 +01:00
Clifford Wolf	97f2979bba	Added commented-out osu025 maping commands to cmos techmap example	2013-11-18 12:01:00 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	404b46674b	Fixed techmap of $reduce_xnor with multi-bit outputs	2013-11-07 00:58:06 +01:00
Clifford Wolf	b41740060b	Fixed techmap of $gt and $ge with multi-bit outputs	2013-11-06 22:59:45 +01:00
Clifford Wolf	6fcbc79b5c	Improved width extension with regard to undef propagation	2013-11-06 21:05:11 +01:00
Clifford Wolf	0b4a64ac6a	Added DFFSR cell to techlibs/cmos/cmos_cells.lib	2013-10-31 12:27:35 +01:00
James Walmsley	40b3551b45	[EXAMPLES] Ported the mojo counter example to Zynq ZED board. ... Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.	2013-10-27 21:48:39 +01:00
Clifford Wolf	88cd2eadf5	Cleanups in xilinx examples	2013-10-27 09:58:53 +01:00
Clifford Wolf	4a3669d871	Added synth_xilinx command	2013-10-27 09:51:06 +01:00
Clifford Wolf	90b016716b	Moved simple xilinx counter sim example to subdir	2013-10-27 09:30:17 +01:00
Clifford Wolf	02f321b6fc	Xilinx mojo_counter example is now working	2013-10-27 08:21:56 +01:00
Clifford Wolf	d635f8adaa	Renamed techlibs/xilinx7 to techlibs/xilinx	2013-10-26 22:29:40 +02:00
Clifford Wolf	4007b41d40	Improved xilinx mojo_counter example	2013-10-26 22:28:42 +02:00
Clifford Wolf	b934a2d209	Added another xilinx example (not funcional yet)	2013-10-26 17:22:29 +02:00
Clifford Wolf	0836a1f2ba	Bugfix in dffsr techmap rules	2013-10-18 13:24:44 +02:00
Clifford Wolf	8197169f8d	Added techmap rules for $sr, $dffsr and $dlatch	2013-10-18 12:29:21 +02:00
Clifford Wolf	e0f693cbb0	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	2013-10-18 12:13:34 +02:00