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Added more generic _TECHMAP_ wire mechanism to techmap pass

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This commit is contained in:
Clifford Wolf 2013-11-23 15:58:06 +01:00
parent 9ab850e45e
commit 532091afcb
3 changed files with 193 additions and 79 deletions
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2
techlibs/xilinx/cells.v
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@ -46,7 +46,7 @@ module \$lut (I, O);
.I0(I[0]), .I1(I[1]), .I2(I[2]),
.I3(I[3]), .I4(I[4]), .I5(I[5]));
end else begin:error
wire TECHMAP_FAIL;
wire _TECHMAP_FAIL_ = 1;
end
endgenerate