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https://github.com/YosysHQ/yosys
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Added "techmap -share_map" option
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parent
019b301541
commit
20175afd29
2 changed files with 13 additions and 4 deletions
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@ -82,7 +82,7 @@ struct SynthXilinxPass : public Pass {
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log(" clean\n");
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log("\n");
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log(" map_cells:\n");
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log(" techmap -map <share_dir>/xilinx/cells.v\n");
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log(" techmap -share_map xilinx/cells.v\n");
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log(" clean\n");
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log("\n");
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log(" clkbuf:\n");
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@ -94,7 +94,7 @@ struct SynthXilinxPass : public Pass {
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log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
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log("\n");
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log(" edif:\n");
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log(" write_edif -top <top> synth.edif\n");
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log(" write_edif synth.edif\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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@ -182,7 +182,7 @@ struct SynthXilinxPass : public Pass {
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if (check_label(active, run_from, run_to, "map_cells"))
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{
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Pass::call(design, stringf("techmap -map %s", get_share_file_name("xilinx/cells.v").c_str()));
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Pass::call(design, "techmap -share_map xilinx/cells.v");
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Pass::call(design, "clean");
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}
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@ -201,7 +201,7 @@ struct SynthXilinxPass : public Pass {
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if (check_label(active, run_from, run_to, "edif"))
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{
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if (!edif_file.empty())
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Pass::call(design, stringf("write_edif -top %s %s", top_module.c_str(), edif_file.c_str()));
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Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
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}
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log_pop();
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