3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00

Added "techmap -share_map" option

This commit is contained in:
Clifford Wolf 2013-11-24 19:50:25 +01:00
parent 019b301541
commit 20175afd29
2 changed files with 13 additions and 4 deletions

View file

@ -82,7 +82,7 @@ struct SynthXilinxPass : public Pass {
log(" clean\n");
log("\n");
log(" map_cells:\n");
log(" techmap -map <share_dir>/xilinx/cells.v\n");
log(" techmap -share_map xilinx/cells.v\n");
log(" clean\n");
log("\n");
log(" clkbuf:\n");
@ -94,7 +94,7 @@ struct SynthXilinxPass : public Pass {
log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
log("\n");
log(" edif:\n");
log(" write_edif -top <top> synth.edif\n");
log(" write_edif synth.edif\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@ -182,7 +182,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_cells"))
{
Pass::call(design, stringf("techmap -map %s", get_share_file_name("xilinx/cells.v").c_str()));
Pass::call(design, "techmap -share_map xilinx/cells.v");
Pass::call(design, "clean");
}
@ -201,7 +201,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "edif"))
{
if (!edif_file.empty())
Pass::call(design, stringf("write_edif -top %s %s", top_module.c_str(), edif_file.c_str()));
Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
}
log_pop();